H8S-2655 Datasheet, PDF (998/1091 Pages) Renesas Technology Corp – 16-Bit Single-Chip Microcomputer

Appendix B Internal I/O Register
SSR1—Serial Status Register 1
H'FF84
Smart Card Interface 1
Bit
:
Initial value :
Read/Write :
7
TDRE
1
R/(W)*
6
RDRF
0
R/(W)*
5
ORER
0
R/(W)*
4
ERS
0
R/(W)*
3
PER
0
R/(W)*
2
TEND
1
R
1
MPB
0
R
0
MPBT
0
R/W
Multiprocessor Bit Transfer
0 Data with a 0 multiprocessor bit is transmitted
1 Data with a 1 multiprocessor bit is transmitted
Multiprocessor Bit
0 [Clearing condition]
When data with a 0 multiprocessor bit is received
1 [Setting condition]
When data with a 1 multiprocessor bit is received
Transmit End
0 [Clearing conditions]
• When 0 is written to TDRE after reading TDRE = 1
• When the DMAC or DTC is activated by a TXI interrupt and write data to TDR
1 [Setting conditions]
• On reset, or in standby mode or module stop mode
• When the TE bit in SCR is 0 and the ERS bit is also 0
• When TDRE = 1 and ERS = 0, 2.5 etu after a 1-byte serial
transmit character is sent (normal transmission)
Note: etu: Elementary Time Unit (the time taken to transmit one bit)
Parity Error
0 [Clearing condition]
When 0 is written to PER after reading PER = 1
1 [Setting condition]
When, in reception, the number of 1 bits in the receive data plus the parity bit
does not match the parity setting (even or odd) specified by the O/E bit in SMR
Error Signal Status
0 [Clearing conditions]
• On reset, or in standby mode or module stop mode
• When 0 is written to ERS after reading ERS =1
1 [Setting condition]
When the error signal is sampled at the low level
Note: Clearing the TE bit in SCR to 0 does not affect the ERS flag, which retains its prior state.
Overrun Error
0 [Clearing condition]
When 0 is written to ORER after reading ORER = 1
1 [Setting condition]
When the next serial reception is completed while RDRF = 1
Receive Data Register Full
0 [Clearing conditions]
• When 0 is written to RDRF after reading RDRF = 1
• When the DMAC or DTC is activated by an RXI interrupt and read data from RDR
1 [Setting condition]
When serial reception ends normally and receive data is transferred
from RSR to RDR
Transmit Data Register Empty
0 [Clearing conditions]
• When 0 is written to TDRE after reading TDRE = 1
• When the DMAC or DTC is activated by a TXI interrupt and write data to TDR
1 [Setting conditions]
• When the TE bit in SCR is 0
• When data is transferred from TDR to TSR and data can be written to TDR
Note: * Can only be written with 0 for flag clearing.
Rev. 5.00 Sep 14, 2006 page 970 of 1060
REJ09B0331-0500