H8S-2655 Datasheet, PDF (671/1091 Pages) Renesas Technology Corp – 16-Bit Single-Chip Microcomputer

Section 14 Serial Communication Interface (SCI)
Table 14.12 SCI Interrupt Sources
Interrupt
Channel Source Description
DTC
DMAC
Activation Activation Priority^*
0
ERI
Interrupt due to receive error
Not
Not
High
(ORER, FER, or PER)
possible possible
RXI
Interrupt due to receive data full
Possible Possible
state (RDRF)
TXI
Interrupt due to transmit data empty Possible Possible
state (TDRE)
TEI
Interrupt due to transmission end Not
Not
(TEND)
possible possible
1
ERI
Interrupt due to receive error
Not
Not
(ORER, FER, or PER)
possible possible
RXI
Interrupt due to receive data full
Possible Possible
state (RDRF)
TXI
Interrupt due to transmit data empty Possible Possible
state (TDRE)
TEI
Interrupt due to transmission end Not
Not
(TEND)
possible possible
2
ERI
Interrupt due to receive error
Not
Not
(ORER, FER, or PER)
possible possible
RXI
Interrupt due to receive data full
Possible Not
state (RDRF)
possible
TXI
Interrupt due to transmit data empty Possible Not
state (TDRE)
possible
TEI
Interrupt due to transmission end Not
Not
(TEND)
possible possible Low
Note: * This table shows the initial state immediately after a reset. Relative priorities among
channels can be changed by means of the interrupt controller.
A TEI interrupt is requested when the TEND flag is set to 1 while the TEIE bit is set to 1. The
TEND flag is cleared at the same time as the TDRE flag. Consequently, if a TEI interrupt and a
TXI interrupt are requested simultaneously, the TXI interrupt may be accepted first, with the
result that the TDRE and TEND flags are cleared. Note that the TEI interrupt will not be accepted
in this case.
Rev. 5.00 Sep 14, 2006 page 643 of 1060
REJ09B0331-0500