H8S-2655 Datasheet, PDF (584/1091 Pages) Renesas Technology Corp – 16-Bit Single-Chip Microcomputer

Section 12 8-Bit Timers
12.3 Operation
12.3.1 TCNT Incrementation Timing
TCNT is incremented by input clock pulses (either internal or external).
Internal Clock
Three different internal clock signals (φ/8, φ/64, or φ/8192) divided from the system clock (φ) can
be selected, by setting bits CKS2 to CKS0 in TCR. Figure 12.2 shows the count timing.
φ
Internal clock
Clock input
to TCNT
TCNT
N–1
N
Figure 12.2 Count Timing for Internal Clock Input
N+1
External Clock
Three incrementation methods can be selected by setting bits CKS2 to CKS0 in TCR: at the rising
edge, the falling edge, and both rising and falling edges.
Note that the external clock pulse width must be at least 1.5 states for incrementation at a single
edge, and at least 2.5 states for incrementation at both edges. The counter will not increment
correctly if the pulse width is less than these values.
Figure 12.3 shows the timing of incrementation at both edges of an external clock signal.
Rev. 5.00 Sep 14, 2006 page 556 of 1060
REJ09B0331-0500