H8S-2655 Datasheet, PDF (546/1091 Pages) Renesas Technology Corp – 16-Bit Single-Chip Microcomputer

Section 10 16-Bit Timer Pulse Unit (TPU)
Contention between TCNT Write and Overflow/Underflow
If there is an up-count or down-count in the T2 state of a TCNT write cycle, and
overflow/underflow occurs, the TCNT write takes precedence and the TCFV/TCFU flag in TSR is
not set.
Figure 10.57 shows the operation timing when there is contention between TCNT write and
overflow.
TCNT write cycle
T1
T2
φ
Address
TCNT address
Write signal
TCNT
H'FFFF
TCNT write data
M
TCFV flag
Figure 10.57 Contention between TCNT Write and Overflow
Multiplexing of I/O Pins
In the H8S/2655 Group, the TCLKA input pin is multiplexed with the TIOCC0 I/O pin, the
TCLKB input pin with the TIOCD0 I/O pin, the TCLKC input pin with the TIOCB1 I/O pin, and
the TCLKD input pin with the TIOCB2 I/O pin. When an external clock is input, compare match
output should not be performed from a multiplexed pin.
Interrupts and Module Stop Mode
If module stop mode is set when an interrupt has been requested, the CPU interrupt source or
DMAC/DTC activation source cannot be cleared. Interrupts should therefore be disabled before
setting module stop mode.
Rev. 5.00 Sep 14, 2006 page 518 of 1060
REJ09B0331-0500