TLV320AIC3204 Datasheet, PDF (98/159 Pages) Texas Instruments – Ultra Low Power Stereo Audio Codec

TLV320AIC3204
Ultra Low Power Stereo Audio Codec
SLOS602A – SEPTEMBER 2008 – REVISED OCTOBER 2008
www.ti.com
Default settings used.
PLL Disabled
DOSR 128
# Initialize to Page 0
w 30 00 00
# Initialize the device through software reset
w 30 01 01
# Power up the NDAC divider with value 1
w 30 0b 81
# Power up the MDAC divider with value 2
w 30 0c 82
# Program the OSR of DAC to 128
w 30 0d 00
w 30 0e 80
# Set the word length of Audio Interface to 20bits PTM_P4
w 30 1b 10
# Set the DAC Mode to PRB_P8
w 30 3c 08
# Select Page 1
w 30 00 01
# Disable Internal Crude AVdd in presence of external AVdd supply or before
#powering up internal AVdd LDO
w 30 01 08
# Enable Master Analog Power Control
w 30 02 00
# Set the REF charging time to 40ms
w 30 7b 01
# HP soft stepping settings for optimal pop performance at power up
# Rpop used is 6k with N = 6 & soft step = 20usec. This should work with 47uF coupling
# capacitor. Can try N=5,6 or 7 time constants as well. Trade-off delay vs “pop” sound.
w 30 14 25
# Set the Input Common Mode to 0.9V and Output Common Mode for Headphone to
# Input Common Mode
w 30 0a 00
# Route Left DAC to HPL
w 30 0c 08
# Route Right DAC to HPR
w 30 0d 08
# Set the DAC PTM mode to PTM_P3/4
w 30 03 00
w 30 04 00
# Set the HPL gain to 0dB
w 30 10 00
# Set the HPR gain to 0dB
w 30 11 00
# Power up HPL and HPR drivers
w 30 09 30
# Wait for 2.5 sec for soft stepping to take effect
# Else read Page 1, Register 63d, D(7:6). When = “11” soft-stepping is complete
# Select Page 0
w 30 00 00
# Power up the Left and Right DAC Channels with route the Left Audio digital data to
# Left Channel DAC and Right Audio digital data to Right Channel DAC
w 30 3f d6
# Unmute the DAC digital volume control
w 30 40 00
5.22.2 Stereo DAC Playback with 48ksps Sample Rate and Low Power Mode
Assumption
AVdd = 1.8V, DVdd = 1.8V
MCLK = 12.288MHz
Ext C = 47µF
Based on C the wait time will change.
Wait time = N*Rpop*C + 4* Offset ramp time
Default settings used.
PLL Disabled
# Initialize to Page 0
w 30 00 00
# Initialize the device through software reset
w 30 01 01
# Power up the NDAC divide with value 1
w 30 0b 81
98
Application Information
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