TLV320AIC3204 Datasheet, PDF (74/159 Pages) Texas Instruments – Ultra Low Power Stereo Audio Codec

TLV320AIC3204
Ultra Low Power Stereo Audio Codec
SLOS602A – SEPTEMBER 2008 – REVISED OCTOBER 2008
www.ti.com
gain change. The rate of soft-stepping can be controlled by programming Page 0, Reg 63, D(1:0) to either
one step per frame ( DAC_FS ) or one step per 2 frames. The soft-stepping feature can also be entirely
disabled. During soft-stepping the value of the actual applied gain would differ from the programmed gain
in register. The TLV320AIC3204 gives a feedback to the user in form of register readable flag to indicate
that soft-stepping is currently in progress. The flags for left and right channels can be read back by
reading Page 0, Reg 38, D(4) and D(0) respectively. A value of 0 in these flags indicates a soft-stepping
operation in progress, and a value of 1 indicates that soft-stepping has completed. A soft-stepping
operation comes into effect during a) power-up, when the volume control soft-steps from –63.5dB to
programmed gain value b) volume change by user when DAC is powered up and c) power-down, when
the volume control block soft-steps to –63.5dB before powering down the channel.
5.13.3 Dynamic Range Compression
Typical music signals are characterized by crest factors, the ratio of peak signal power to average signal
power, of 12dB or more. In order to avoid audible distortions due to clipping of peak signals, the gain of
the DAC channel must be adjusted so as not to cause hard clipping of peak signals. As a result, during
nominal periods, the applied gain is low, causing the perception that the signal is not loud enough. To
overcome this problem, the DRC in the TLV320AIC3204 continuously monitors the output of the DAC
Digital Volume control to detect its power level w.r.t. 0dB FS. When the power level is low, it increases the
input signal gain to make it sound louder. At the same time, if a peaking signal is detected, it
autonomously reduces the applied gain to avoid hard clipping. This results in sounds more pleasing to the
ear as well as sounding louder during nominal periods.
The DRC functionality in the TLV320AIC3204 is implemented by a combination of Processing Blocks in
the DAC channel as described in Section 5.11.2.
The DRC can be disabled by writing into Page 0, Reg 68, D(6:5).
The DRC typically works on the filtered version of the input signal. The input signals have no audio
information at DC and extremely low frequencies; however they can significantly influence the energy
estimation function in DRC. Also most of the information about signal energy is concentrated in the low
frequency region of the input signal.
In order to estimate the energy of the input signal, the signal is first fed to the DRC high-pass filter and
then to the DRC low-pass filter. These filters are implemented as first-order IIR filters given by
H_HPF (z)
=
N₀
2 ²³
+ N₁z ^-1
- D₁z ^-1
(5-11)
H_LPF (z)
=
N₀ + N₁z ^-1
2²³ - D₁z ^-1
(5-12)
The coefficients for these filters are 24-bits wide in two’s-complement and are user programmable through
register write as given in Table 5-21
Coefficient
HPF N0
HPF N1
HPF D1
LPF N0
LPF N1
LPF D1
Table 5-21. DRC HPF and LPF Coefficients
Location
C71 Page 46, Register 52 to 55
C72 Page 46, Register 56 to 59
C73 Page 46, Register 60 to 63
C74 Page 46, Register 64 to 67
C75 Page 46, Register 68 to 71
C76 Page 46, Register 72 to 75
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Application Information
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