TLV320AIC3204 Datasheet, PDF (24/159 Pages) Texas Instruments – Ultra Low Power Stereo Audio Codec

TLV320AIC3204
Ultra Low Power Stereo Audio Codec
SLOS602A – SEPTEMBER 2008 – REVISED OCTOBER 2008
Description
Required Register Setting
G8
I²S ADC word clock input
on pin 8, SCLK/MFP3
Pg 0, Reg 56, D(2:1)=01
Pg 0, Reg 31, D(2:1)=01
G32
I²S ADC word clock input
on pin 32 GPIO/MFP5
Pg 0, Reg 52, D(5:2)=0001
Pg 0, Reg 31, D(2:1)=00
H11
I²S ADC WCLK out on pin
11 MISO/MFP4
Pg 0, Reg 55, D(4:1)=0110
H32
I²S ADC WCLK out on pin
32 GPIO/MFP5
Pg 0, Reg 52, D(5:2)=0111
I4
I²S DIN on pin 4,
DIN/MFP1
Pg 0, Reg 54, D(2:1)=01
J5
I²S DOUT on pin 4,
DOUT/MFP2
Pg 0, Reg 53, D(3:1)=001
K5
General Purpose Out I on
pin 5, DOUT/MFP2
Pg 0, Reg 53, D(3:1)=010
K11
General Purpose Out II on
pin 11, MISO/MFP4
Pg 0, Reg 55, D(4:1)=0010
K32
General Purpose Out III on
pin 32, GPIO/MFP5
Pg 0, Reg 52, D(5:2)=0011
L4
General Purpose In I on pin
4, DIN/MFP1
Pg 0, Reg 54, D(2:1)=10
L8
General Purpose In II on
pin 8, SCLK/MFP3
Pg 0, Reg 56, D(2:1)=10
L32
General Purpose In III on
pin 32, GPIO/MFP5
Pg 0, Reg 52, D(5:2)=0010
M5
INT1 output on pin 5,
DOUT/MFP2
Pg 0, Reg 53, D(3:1)=100
M11
INT1 output on pin 11,
MISO/MFP4
Pg 0, Reg 55, D(4:1)=0100
M32
INT1 output on pin 32,
GPIO/MFP5
Pg 0, Reg 52, D(5:2)=0101
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Description
Required Register
Setting
Pg 0, Reg 52,
R32
Secondary I²S WCLK in on pin 32, D(5:2)=0001
GPIO/MFP50
Pg 0, Reg 31,
D(4:3)=0
S8
Secondary I²S DIN on pin 8,
SCLK/MFP3
Pg 0, Reg 56,
D(2:1)=01
Pg 0, Reg 31,0=1
S32
Secondary I²S DIN on pin 32,
GPIO/MFP5
Pg 0, Reg 52,
D(5:2)=0001
Pg 0, Reg 31,0=0
T11
Secondary I²S DOUT on pin 11,
MISO/MFP4
Pg 0, Reg 55,
D(4:1)=1000
U5
Secondary I²S BCLK OUT on pin Pg 0, Reg 53,
5, DOUT/MFP2
D(3:1)=110
U11
Secondary I²S BCLK OUT on pin Pg 0, Reg 55,
11, MISO/MFP4
D(4:1)=1001
U32
Secondary I²S BCLK OUT on pin Pg 0, Reg 52,
32, GPIO/MFP5
D(5:2)=1000
V5
Secondary I²S WCLK OUT on pin Pg 0, Reg 53,
5, SCLK/MFP3
D(3:1)=111
V11
Secondary I²S WCLK OUT on pin Pg 0, Reg 55,
11, MISO/MFP4
D(4:1)=1010
V32
Secondary I²S WCLK OUT on pin Pg 0, Reg 52,
32, GPIO/MFP5
D(5:2)=1001
W8
Headset Detect Input on pin 8,
SCLK/MFP3
Pg 0, Reg 56,
D(2:1)=00
Pg 0,67,7=1
X5
Aux Clock Output on pin 5,
DOUT/MFP2
Pg 0, Reg 53,
D(3:1)=011
X11
Aux Clock Output on pin 11,
MISO/MFP4
Pg 0, Reg 55,
D(4:1)=0011
X32
Aux Clock Output on pin 32,
GPIO/MFP5
Pg 0, Reg 52,
D(5:2)=0100
24
Application Information
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