DF2138AFA20 Datasheet, PDF (968/1063 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Appendix B Internal I/O Registers
ICCR1—I²C Bus Control Register 1
ICCR0—I²C Bus Control Register 0
Bit
7
ICE
Initial value
0
Read/Write R/W
6
5
IEIC MST
0
0
R/W R/W
H'FF88
H'FFD8
IIC1
IIC0
4
TRS
0
R/W
3
ACKE
0
R/W
2
BBSY
0
R/W
1
IRIC
0
R/(W)*
0
SCP
1
W
Start condition/stop condition
prohibit
0 Writing 0 issues a start or
stop condition, in combination
with the BBSY flag
1 Reading always returns a
value of 1; writing is ignored
I²C bus interface interrupt request flag
0 Waiting for transfer, or transfer in
progress
1 Interrupt requested
Note: For the clearing and setting
conditions, see section 16.2.5,
I²C Bus Control Register (ICCR).
Bus busy
I²C bus interface interrupt
enable
0 Interrupts disabled
1 Interrupts enabled
0 Bus is free
[Clearing condition]
When a stop condition is detected
1 Bus is busy
[Setting condition]
When a start condition is detected
Acknowledge bit judgement selection
I²C bus interface enable
0 I²C bus interface module disabled, with
SCL and SDA signal pins set to port
function
Internal state initialization of I²C bus
interface module
SAR and SARX can be accessed
1 I²C bus interface module enabled for
transfer operations (pins SCL and SCA
are driving the bus)
ICMR and ICDR can be accessed
Note: * Only 0 can be written, to clear the flag.
0 The value of the acknowledge bit is ignored,
and continuous transfer is performed
1 If the acknowledge bit is 1, continuous
transfer is interrupted
Master/slave select (MST), transmit/receive select (TRS)
0 0 Slave receive mode
1 Slave transmit mode
1 0 Master receive mode
1 Master transmit mode
Note: For details, see section 16.2.5, I²C Bus Control
Register (ICCR).
Rev. 4.00 Jun 06, 2006 page 912 of 1004
REJ09B0301-0400