DF2138AFA20 Datasheet, PDF (827/1063 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 25 Electrical Characteristics
(3) Bus Timing
Table 25.33 shows the bus timing. Operation in external expansion mode is not guaranteed when
operating on the subclock (φ = 32.768 kHz).
Table 25.33 Bus Timing
Condition A: V_CC = 5.0 V ±10%, V_SS = 0 V, φ = 2 MHz to maximum operating frequency,
T_a = –20 to +75°C (regular specifications),
T_a = –40 to +85°C (wide-range specifications)
Condition B: V_CC = 4.0 V to 5.5 V, V_SS = 0 V, φ = 2 MHz to maximum operating frequency,
T_a = –20 to +75°C (regular specifications),
T_a = –40 to +85°C (wide-range specifications)
Condition C: V_CC = 2.7 V to 5.5 V (mask ROM version), V_CC = 3.0 V to 5.5 V (F-ZTAT version),
V_SS = 0 V, φ = 2 MHz to maximum operating frequency,
T_a = –20 to +75°C
Item
Address
delay time
Address
setup time
Address
hold time
CS delay
time (IOS)
AS delay
time
RD delay
time 1
RD delay
time 2
Read data
setup time
Read data
hold time
Condition A
20 MHz
Symbol Min Max
t_AD
—
20
t_AS
0.5 × —
t_cyc –15
t_AH
0.5 × —
t_cyc –10
t_CSD
—
20
t_ASD
—
30
t
—
30
RSD1
t_RSD2
—
30
t
15
—
RDS
t_RDH
0
—
Condition B
16 MHz
Min Max
—
30
0.5 × —
t_cyc –20
0.5 × —
t_cyc –15
—
30
—
45
—
45
—
45
20
—
0
—
Condition C
10 MHz
Min Max
—
40
0.5 × —
t_cyc –30
0.5 × —
t_cyc –20
—
40
Test
Unit Conditions
ns Figure
25.10 to
ns ^figure
25.14
ns
ns
—
60
ns
—
60
ns
—
60
ns
35
—
ns
0
—
ns
Rev. 4.00 Jun 06, 2006 page 771 of 1004
REJ09B0301-0400