DF2138AFA20 Datasheet, PDF (275/1063 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Port 5 Data Direction Register (P5DDR)
Section 8 I/O Ports
Bit
7
—
Initial value
1
Read/Write
—
6
5
—
—
1
1
—
—
4
3
2
1
0
—
— P52DDR P51DDR P50DDR
1
1
0
0
0
—
—
W
W
W
P5DDR is an 8-bit write-only register, the individual bits of which specify input or output for the
pins of port 5. P5DDR cannot be read; if it is, an undefined value will be returned. Bits 7 to 3 are
reserved.
Setting a P5DDR bit to 1 makes the corresponding port 5 pin an output pin, while clearing the bit
to 0 makes the pin an input pin.
P5DDR is initialized to H'F8 by a reset and in hardware standby mode. It retains its prior state in
software standby mode. As SCI0 is initialized, the pin states are determined by the IIC0 ICCR,
P5DDR, and P5DR specifications.
Port 5 Data Register (P5DR)
Bit
7
6
5
4
3
2
1
0
—
—
—
—
— P52DR P51DR P50DR
Initial value
1
1
1
1
1
0
0
0
Read/Write
—
—
—
—
—
R/W
R/W
R/W
P5DR is an 8-bit readable/writable register that stores output data for the port 5 pins (P52 to P50).
If a port 5 read is performed while P5DDR bits are set to 1, the P5DR values are read directly,
regardless of the actual pin states. If a port 5 read is performed while P5DDR bits are cleared to 0,
the pin states are read.
Bits 7 to 3 are reserved; they cannot be modified and are always read as 1.
P5DR is initialized to H'F8 by a reset and in hardware standby mode. It retains its prior state in
software standby mode.
Rev. 4.00 Jun 06, 2006 page 219 of 1004
REJ09B0301-0400