R8A66593FPBG_15 Datasheet, PDF (92/144 Pages) Renesas Technology Corp – ASSP (USB2.0 Peripheral Controller)

R8A66593FP/BG
Register
Name
PIPExTRE
PIPExTRN
Bit Name
TRENB
TRCLR
TRNCNT
Setting Description
Comments
Transaction count enable
Current transaction
counter clear
Transaction counter
PIPE1-5: can be set
Refer to 2.18.1 for more details.
PIPE1-5: can be set
Refer to 2.18.2 for more details.
PIPE1-5: can be set
Refer to 2.18.3 for more details.
3.3.1
Maximum Packet Size Setting
Maximum packet size for each pipe is set in the MXPS bit of the DCPMAXP and PIPEMAXP registers. DCP and pipes
1-5 can be set with any maximum packet size defined in the USB specifications. Pipes 6-9 are limited to maximum
packet size of 64 bytes. Set the maximum packet size before starting transfers (set “PID=BUF”).
DCP: set to “64” for Hi-Speed operation
DCP: set to “8”, “16”, “32”, or “64” for Full-Speed operation
PIPE 1-5: set to “512” for Hi-Speed bulk transfer
PIPE 1-5: set to “8”, “16”, “32”, or “64” for Full-Speed bulk transfer
PIPE 1-2: set a value from “1” to “1024” for Hi-Speed isochronous transfer
PIPE: 1-2: set a value from “1” to “1023” for Full-Speed isochronous transfer. For more details, see section 3.9.
PIPE 6-9: Set a value from “1” to “64”.
High-bandwidth transfers are not yet supported in interrupt and isochronous transfers.
3.3.2
Response PID
Set the response PID for each pipe with the PID bit of the DCPCTR and PIPExCTR registers.
The response PID specifies the response to a transaction from the Host.
(a) NAK setting: Always sends a NAK response when a transaction is issued.
(b) BUF setting: Responds to the transaction in accordance with the buffer memory status.
(c) STALL setting: Always sends a STALL response when a transaction is issued.
Regardless of the value set in the PID bit, an ACK is always sent as a response to a setup transaction and the
USB request is stored in corresponding registers.
Based on the results of the transaction, the controller may trigger the PID bit to be written.
The controller will trigger a write event to the PID bit in the following cases.
(a) NAK Setting:
(i) When SETUP token is received normally (only DCP)
(ii) In bulk transfers when PIPECFG register SHTNAK bit is set to “1” and short packet is received
(iii) In bulk transfers when SHTNAK bit is set to “1” and the transfaction counter is completed.
(b) BUF setting: the BUF cannot be written by the controller
(c) STALL setting:
(i) When a maximum packet size over error is detected for a received data packet
(ii) When a control transfer sequence error is detected
R19DS0071EJ0101 Rev1.01
Jun 28,2013
Page 92 of 142