R8A66593FPBG_15 Datasheet, PDF (73/144 Pages) Renesas Technology Corp – ASSP (USB2.0 Peripheral Controller)

R8A66593FP/BG
2.18 Transaction counter
♦ Pipe1 Transaction counter enabled register [PIPE1TRE]
<Address: 90H>
♦ Pipe2 Transaction counter enabled register [PIPE2TRE]
<Address: 94H>
♦ Pipe3 Transaction counter enabled register [PIPE3TRE]
<Address: 98H>
♦ Pipe4 Transaction counter enabled register [PIPE4TRE]
<Address: 9CH>
♦ Pipe5 Transaction counter enabled register [PIPE5TRE]
<Address: A0H>
15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
TRENB TRCLR
?
?
?
?
?
?
0
0
?
?
?
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-
-
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Bit
Name
15-10 Unassigned. Fix to "0".
9
TRENB
Transaction counter enabled
8
TRCLR
Transaction counter clear
7-0 Unassigned. Fix to "0"."
Function
Software Hardware Remarks
Specifies whether the transaction counter is
invalid/valid.
0: Transaction counter function invalid
1: Transaction counter function valid
R/W
R
Transaction counter can be cleared to "0" by writing "1"
to this bit.
0: Invalid
R(0)/W(1) R
1: Count counter clear
Remarks
* Not modify each bit of the register except when "PID=NAK". To modify each bit after modifying the PID bit of the pipe from
"BUF" to "NAK", check that "PBUSY=0", and then modify it. However, when the controller modifies PID bit to "NAK", it is not
necessary to check the PBUSY bit.
2.18.1 Transaction counter enabled bit (TRENB)
For the reception pipe, after the total number of packets is written to the TRNCNT bit using the software, the controller
executes the following control on receiving the same number of packets as the setup value of the TRNCNT bit:
(1) When the continuous transmission/reception mode is used (write "CNTMD=1"), toggles on CPU side even if the
FIFO buffer is not full when reception is completed.
(2) If writing "SHTNAK=1", modifies the pipe PID bit to "NAK".
(3) If writing "DENDE=1" and "PKTMD=0", asserts the DEND signal while reading the last data.
(4) If writing "BFRE=1", asserts the BRDY interrupt.
Regarding the transmission pipe, write "0" to this bit. When the transaction count function is not used, write "0" to this
bit. When the transaction count function is used, set the TRNCNT bit before writing "1" to this bit. Also write "1" to this
bit before receiving the initial packet that is the transaction target.
2.18.2 Transaction counter clear bit (TRCLR)
If the software writes "1" to this bit, the controller clears the current count value of the transaction counter
corresponding to the pipe and sets "0" in this bit.
R19DS0071EJ0101 Rev1.01
Jun 28,2013
Page 73 of 142