R8A66593FPBG_15 Datasheet, PDF (11/144 Pages) Renesas Technology Corp – ASSP (USB2.0 Peripheral Controller)

R8A66593FP/BG
2 Register
Design of Register Table
 Bit number:
Each register is connected to the 16-bit internal bus. Odd address are from b15 to b8, and even address are from b7 to b0.
 Status after reset:
Indicates the register initial status immediately after the reset operation.
A hardware reset is the initialization status when the external reset signal is entered from the RST_N pin.
A USB bus reset is the initialization status when a USB bus reset is detected by the controller.
Significant points in the reset operation are mentioned in the notes.
"-" indicates the status of retained user settings without any controller operations.
"?" indicates the status when the value is not determined.
 Software access conditions:
Conditions when the register is accessed by the software.
 Hardware access conditions:
Conditions when the register is accessed by the controller during operations other than reset:
R……Read only
W……Write only
R/W…Read/Write
R(0)…"0" Read only
W(1)…"1" Write only
 Remarks:
Remarks and detailed description item number.
 Name:
This is the bit symbol and bit name.
 Function:
This is the description of the function. When there is no particular rejection, the value during read is the value written by the
software or hardware.
Example:
The shaded portions are unassigned. Fix to"0".
 Bit Number
→ 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Bit Symbol
→
A bit B bit C bit
 Hardware reset → ? 0 0 0
USB bus reset → ? 0 - -
Bit
Name
Function
15 Unassigned. Fix to "0".
14
A bit
AAA enabled
0: Operations disabled
1: Operations enabled
13
B bit
BBB operation
0: Low output
1: High output
12
C bit
CCC control
0: 
1: 


Software Hardware Remarks
R/W
R
R
W
R(0)/W(1)
R



Remarks
R19DS0071EJ0101 Rev1.01
Jun 28,2013
Page 11 of 142