32185 Datasheet, PDF (914/1032 Pages) Renesas Technology Corp – MCU

22
POWER SUPPLY CIRCUIT
22.3 Power-Off Sequence
22.3.2 Power-Off Sequence when Using RAM Backup
The diagram below shows a turn-off sequence of the power supply (5.0 V or 3.3 V) when using RAM
backup with HREQ function.
VCCE, VCCER,
VCC-BUS
AVCC0
VREF0
P72/HREQ#
RESET#
(Note 1)
(Note 2)
(Note 3)
VDDE
0V
0V
0V
0V
0V
(Note 4)
3V
Note 1: Pull the HREQ# input pin "L" to halt the CPU at the end of the bus cycle.
Or disable RAM access in software. P72 can be used as HREQ# irrespective of the operation mode.
However, HREQ# must be selected with the Port Operation Mode Register for P72.
Note 2: Pull the RESET# input pin "L" while the CPU is halted or RAM access is disabled.
Note 3: Wait until the RESET# pin goes "L" before turning the power supply off.
Note 4: Lower the VDDE voltage to 3.0 V as necessary.
Notes: • Power-off limitation
VDDE>=VCCER
In addtion, when VDDE is more than 3.0V, it is not problem even if it cannot fulfill a restrictions (VDDE>=VCCER).
• However, if it cannot fulfill a restrictions (VDDE>=VCCER) when Power-On, sufficient evaluation must be made
during system design in order to ensure that no power will be applied to the microcomputer with a potential difference
of 1 V or more.
For potential differences 0 V to 0.6 V, there is almost no in-flow current. The amount of in-flow current begins to
increase when the potential difference exceeds 0.6 V.
Figure 22.3.2 Power-Off Sequence when Using RAM Backup (VCCE = VDDE = 5.0 V or 3.3 V)
32185/32186 Group Hardware Manual
Rev.1.10 REJ09B0235-0110 May 15, 07
22-6