32185 Datasheet, PDF (276/1032 Pages) Renesas Technology Corp – MCU

9
DMAC
9.2 DMAC Related Registers
9.2.3 DMA Source Address Registers
DMA0 Source Address Register (DM0SA)
DMA1 Source Address Register (DM1SA)
DMA2 Source Address Register (DM2SA)
DMA3 Source Address Register (DM3SA)
DMA4 Source Address Register (DM4SA)
DMA5 Source Address Register (DM5SA)
DMA6 Source Address Register (DM6SA)
DMA7 Source Address Register (DM7SA)
DMA8 Source Address Register (DM8SA)
DMA9 Source Address Register (DM9SA)
<Address: H’0080 0412>
<Address: H’0080 0422>
<Address: H’0080 0432>
<Address: H’0080 0442>
<Address: H’0080 0452>
<Address: H’0080 041A>
<Address: H’0080 042A>
<Address: H’0080 043A>
<Address: H’0080 044A>
<Address: H’0080 045A>
b0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 b15
DM0SA–DM9SA
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
<Upon exiting reset: Undefined>
b
Bit Name
Function
RW
0–15
DM0SA–DMA9SA
Source address bits A16–A31
(Note 1)
Note 1: A0 to A15 are fixed by DMAn Channel Control Register 1 (DMnCNT1) bits 8 and 9.
Notes: • This register must always be accessed in halfwords.
• Address other than SFR area and internal RAM area must be set.
RW
The DMA Source Address Register is used to set the source address of DMA transfer in such a way that bit
0 and bit 15 correspond to A16 and A31, respectively. Because this register is comprised of a current
register, the values read from this register are always the current value.
When DMA transfer finishes (i.e., the Transfer Count Register underflows), the value in this register if
“Address fixed” is selected, is the same source address that was set in it before the DMA transfer began;
if “Address incremental” is selected, the value in this register is the last transfer address + 1 (for 8-bit
transfer) or the last transfer address + 2 (for 16-bit transfer).
The DMA Source Address Register must always be accessed in halfwords (16 bits) beginning with an even
address. If accessed in bytes, the value in this register is undefined.
(1) DM0SA–DM9SA (Source Address bits A16–A31)
Set this register to specify the source address of DMA transfer in the SFR area or internal RAM area.
For high-order 16 bits (A0 to A15) of the source address, Bank 0 to Bank 2 are selected according to
the setting of DMAn channel control register 1 (DMnCNT1) bits 8 and 9, and the high-order 16 bits of
the corresponding source address are fixed. In this register, the low-order 16 bits of the source
address are set. (Bit 0 and bit 15 correspond to A16 and A31 of the source address, respectively)
Note that no transfer over the bank is carried out when "increment" is selected in SADSLn bit of DMAn
channel control register(DMnCNT0). Upon completion of bank transfer to the final address, the bank
is to be transferred to the head address.
32185/32186 Group Hardware Manual
Rev.1.10 REJ09B0235-0110 May 15, 07
9-30