32185 Datasheet, PDF (863/1032 Pages) Renesas Technology Corp – MCU

18
WAIT CONTROLLER
18.3 Typical Operation of Wait Controller
Bus Mode Control Register (Note 1)
BUSMOD bit = 1 (byte enable separated)
CS Area Wait Control Register (Note 2)
WAIT bit = 0001 (1 wait)
CWAIT bit = 0 (without CS wait)
SWAIT bit = 0 (without strobe wait)
RECOV bit = 0 (without recovery cycle)
IDLE bit = 0 (without idle cycle)
Read
CLKOUT
A9–A30
Read (2 cycles)
Internal
1 wait state
CS0#–CS3#
RD#
WR#
"H"
BHE#, BLE#
DB0–DB15
WAIT#
(Don't Care)
(Don't Care)
"H"
Write
CLKOUT
A9–A30
Write (2 cycles)
Internal
1 wait state
CS0#–CS3#
RD#
"H"
WR#
BHE#, BLE#
DB0–DB15
WAIT#
(Don't Care)
(Don't Care)
"H"
Note 1: For details about the Bus Mode Control Register, see Section 17.2.2, "Bus Mode Control Register."
Note 2: For details about the CS Area Wait Control Register, see Section 18.2.1, "CS Area Wait Control Registers."
Notes: • Circles in the above diagram indicate the sampling timing.
• CLKOUT is not output.
Figure 18.3.15 Read/Write Timing (for Access with Internal 1 Wait State)
32185/32186 Group Hardware Manual
Rev.1.10 REJ09B0235-0110 May 15, 07
18-21