PD46365092B_15 Datasheet, PDF (9/36 Pages) Renesas Technology Corp – 36M-BIT QDRTM II SRAM 2-WORD BURST OPERATION

μPD46365092B, μPD46365182B, μPD46365362B
Power-On Sequence in QDR II SRAM
QDR II SRAMs must be powered up and initialized in a predefined manner to prevent undefined operations.
The following timing charts show the recommended power-on sequence.
The following power-up supply voltage application is recommended: VSS, VDD, VDDQ, VREF, then VIN. VDD and VDDQ
can be applied simultaneously, as long as VDDQ does not exceed VDD by more than 0.5 V during power-up. The
following power-down supply voltage removal sequence is recommended: VIN, VREF, VDDQ, VDD, VSS. VDD and VDDQ
can be removed simultaneously, as long as VDDQ does not exceed VDD by more than 0.5 V during power-down.
Power-On Sequence
Apply power and tie DLL# to HIGH.
Apply V_DDQ before V_REF or at the same time as V_REF.
Provide stable clock for more than 20 μs to lock the PLL.
Continuous min.4 NOP(R# = high) cycles are required after PLL lock up is done.
PLL Constraints
The PLL uses K clock as its synchronizing input and the input should have low phase jitter which is specified as
TKC var. The PLL can cover 120 MHz as the lowest frequency. If the input clock is unstable and the PLL is
enabled, then the PLL may lock onto an undesired clock frequency.
Power-On Waveforms
VDD/VDDQ
DLL#
Clock
R#
VDD/VDDQ Stable (< ±0.1 V DC per 50 ns)
Fix HIGH (or tied to VDDQ)
Unstable Clock
20 μs or more
Stable Clock
4 Times NOP
Normal Operation
Start
R10DS0089EJ0400 Rev.4.00
Nov 09, 2012
Page 9 of 35