PD46365092B_15 Datasheet, PDF (20/36 Pages) Renesas Technology Corp – 36M-BIT QDRTM II SRAM 2-WORD BURST OPERATION

μPD46365092B, μPD46365182B, μPD46365362B
Read and Write Timing
READ WRITE READ WRITE READ WRITE NOP WRITE NOP
1
2
3
4
5
6
7
8
9
10
K
TKHKL TKLKH
TKHKH
TKHK#H TK#HKH
K#
R#
W#
Address
Data in
Data out
CQ
CQ#
C
C#
TIVKH
TKHIX
A0
A1
A2
A3
A4
A5
A6
TAVKH
TKHAX
TKHAX TAVKH
D10
D11
D30
D31
D50
D51
D60
D61
TDVKH TKHDX
Q00
TDVKH TKHDX
Q01
Q20 Q21 Q40
TCHQX1
TCHQX TCHQX
TCQHQX
TCHQV TCHQV TCQHQV
Q41
TCHQZ
TKHCH
TCHCQX
TCHCQV
TCHCQX
TCHCQV
TCQHCQ#H TCQ#HCQH
TKHKL TKLKH TKHK#H
TKHKH
TK#HKH
TKHCH
Remarks 1. Q00 refers to output from address A0+0.
Q01 refers to output from the next internal burst address following A0,i.e.,A0+1.
2. Outputs are disabled (high impedance) 2.5 clock cycles after the last READ (R# = LOW) is input in the
sequences of [READ/WRITE]-[NOP/WRITE], [READ/WRITE]-[NOP/NOP], [READ/NOP]-
[NOP/WRITE] and [READ/NOP] -[NOP/NOP].
3. In this example, if address A0 = A1, data Q00 = D10, Q01 = D11.
Write data is forwarded immediately as read results.
R10DS0089EJ0400 Rev.4.00
Nov 09, 2012
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