HD49340NP Datasheet, PDF (9/22 Pages) Renesas Technology Corp – CDS/PGA & 10-bit A/D Converter

HD49340NP/HNP
Timing Chart
Figure 2 shows the timing chart when CDSIN and ADCIN input modes are used.
0
1
2
~
9
10
11
• When CDSIN input mode is used
CDSIN
N
N+1
N+2
N+9
N+10
N+11
SPBLK
SPSIG
ADCLK
D0 to D9
N−10
N−9
N−8
N−1
N
• When ADCIN input mode is used
N
ADCIN
N+1
N+2
N+10
N+11
N+8
N+9
ADCLK
D0 to D9
N−9
N−8
N−1
N
N+1
Note: The phases of SPBLK and SPSIG are those when the serial data SPinv bit is set to low.
Figure 2 Output Timing Chart when CDSIN and ADCIN Input Modes are Used
• The ADC output (D0 to D9) is output at the rising edge of the ADCLK in both modes.
• Pipe-line delay is ten clock cycles when CDSIN is used and nine when ADCIN is used.
• In ADCIN input mode, the input signal is sampled at the rising edge of the ADCLK.
Rev.1.0 Apr 20, 2004 page 9 of 21