HD49340NP Datasheet, PDF (7/22 Pages) Renesas Technology Corp – CDS/PGA & 10-bit A/D Converter

HD49340NP/HNP
6. ADC Digital Output Control Function
The ADC digital output includes the functions output enable, code conversion, and test mode. Tables 3, 4 and 5
show the output functions and the codes.
Table 3 ADC Digital Output Functions
ADC Digital Output
H X X X X X Hi-Z
D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Operating Mode
Low-power wait state
L L L L L H Same as in table 4.
Normal operation
L H H D9 is inverted in table 4.
H L H D8 to D0 are inverted in table 4.
H H H D9 to D0 are inverted in table 4.
X X L Output code is set up to Clamp Level.
Pre-blanking
H L L H Same as in table 5.
Normal operation
L H H D9 is inverted in table 5.
H L H D8 to D0 are inverted in table 5.
H H H D9 to D0 are inverted in table 5.
X X L Output code is set up to Clamp Level.
Pre-blanking
HXL LX
LHX
H L H L H L H L H L Test mode
L LHLHLHLHL
HLX
HH L H L H L H L H
HHX
LHLHLHLHLH
Notes: 1. STBY, TEST, LINV, and MINV are set by register.
2. Mode setting for the PBLK is done by external input pins.
3. The polarity of the PBLK pin when the register setting is SPinv is low.
Table 4 ADC Output Code
Output Pin
Output Steps
codes
3
4
5
6
511
512
1020
1021
1022
1023
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
L
L
L
L
L
L
L
L
H
H
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
L
L
H
L
H
L
L
L
L
L
L
L
H
H
L
L
H
H
H
H
H
H
H
H
H
H
L
L
L
L
L
L
L
L
L
H
H
H
H
H
H
H
H
L
L
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
Table 5 ADC Output Code (TEST1)
Output Pin
Output Steps
codes
3
4
5
6
511
512
1020
1021
1022
1023
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
L
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
L
H
H
L
L
L
L
L
L
L
L
H
H
H
L
L
L
L
L
L
L
H
L
H
L
H
L
L
L
L
L
L
L
L
H
H
L
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
H
L
H
L
L
L
L
L
L
L
H
H
H
L
L
L
L
L
L
L
L
H
H
L
L
L
L
L
L
L
L
L
Rev.1.0 Apr 20, 2004 page 7 of 21