HD49340NP Datasheet, PDF (6/22 Pages) Renesas Technology Corp – CDS/PGA & 10-bit A/D Converter

HD49340NP/HNP
2. PGA Circuit
The PGAMP is the programmable gain amplifier for the latter stage. The PGAMP and the CDSAMP set the gain
using 8 bits of register.
The equation below shows how the gain changes when register value N is from 0 to 255.
In CDSIN mode: Gain = (–2.36 dB + 0.132 dB) × N (LOG linear).
In ADCIN mode: Gain = (0.57 times + 0.00446 times) × N (linear).
Full-scale digital output is defined as 0 dB (one time) when 1 V is input.
3. Automatic Offset Calibration Function and Black-Level Clamp Data Setting
The DAC DC voltage added to the output of the PGAMP is adjusted by automatic offset calibration.
The data, which cancels the output offset of the PGAMP and the input offset of the ADC, and the clamp data (14
LSB to 76 LSB) set by register are added and input to the DAC.
The automatic offset calibration starts automatically after the RESET mode set by register 1 is cancelled and
terminates after 40000 clock cycles (when fclk = 20 MHz, 2 ms).
4. DC Offset Compensation Feedback Function
Feedback is done to set the black signal level input during the OB period to the DC standard, and all offsets
(including the CCD offset and the CDSAMP offset) are compensated for.
The offset from the ADC output is calculated during the OB period, and SHAMP feedback capacitor C3 is charged
by the current DAC (see figure 1).
The open-loop differential gain (∆Gain/∆H) per 1 H of the feedback loop is given by the following equation. 1H is
the one cycle of the OBP.
∆Gain/∆H = 0.078/(fclk × C3) (fclk: ADCLK frequency, C3: SHAMP external feedback capacitor)
Example:When fclk = 20 MHz and C3 = 1.0 µF, ∆Gain/∆H = 0.0039
When the PGAMP gain setting is changed, the high-speed lead-in operation state is entered, and the feedback loop
gain is increased by a multiple of N. Loop gain multiplication factor N can be selected from 4 times, 8 times, 16
times, or 32 times by changing the register settings (see table 1). Note that the open-loop differential gain
(∆Gain/∆H) must be one or lower. If it is two or more, oscillation occurs.
The time from the termination of high-speed lead-in operation to the return of normal loop gain operation can be
selected from 1 H, 2 H, 4 H, or 8 H. If the offset error is over 32 LSB, the high-speed lead-in operation continues,
and when the offset error is 32 LSB or less, the operation returns to the normal loop-gain operation after 1 H, 2 H, 4
H, or 8 H depending on the register settings. See table 2.
Table 1 Loop Gain Multiplication Factor during
High-Speed Lead-In Operation
HGain-Nsel
(register settings)
[0]
[1]
Multiplication
Factor N
L
L
4
H
L
8
L
H
16
H
H
32
Table 2 High-Speed Lead-In Operation
Cancellation Time
HGstop-Hsel
(register settings)
[0]
[1]
Cancellation
Time
L
L
1H
H
L
2H
L
H
4H
H
H
8H
5. Pre-Blanking Function
During the PBLK input period, the CDS input operation is separated and protected from the large input signal. The
ADC digital output is fixed to clamp data (14 to 76 LSB).
Rev.1.0 Apr 20, 2004 page 6 of 21