HD404449 Datasheet, PDF (9/125 Pages) Hitachi Semiconductor – HD404449 SERIES

HD404449 Series
0
RAM-mapped registers
64
Memory registers (MR)
80
Not used
144
$000
$040
$050
$090
Data (464 digits × 2)
Note
V = 0 (bank 0)
V = 1 (bank 1)
608
752
960
1023
Data (144 digits)
Not used
Stack (64 digits)
$260
$2F0
$3C0
$3FF
$090
Data
(464 digits)
V=0
(bank = 0)
Data
(464 digits)
V=1
(bank = 1)
$25F
Note: The data area has two banks:
bank 0 (V = 0) to bank 1 (V = 1)
R: Read only
W: Write only
R/W: Read/Write
* Two registers are mapped
on the same area.
0
Interrupt control bits area
$000
3
$003
4 Port mode register A
(PMRA) W $004
5 Serial mode register 1A (SM1A) W $005
6 Serial data register 1 lower (SR1L) R/W $006
7 Serial data register 1 upper (SR1U) R/W $007
8 Timer mode register A
(TMA) W $008
9 Timer mode register B1 (TMB1) W $009
10 Timer B
11
(TRBL/TWBL) R/W $00A
*
(TRBU/TWBU) R/W $00B
12 Miscellaneous register
(MIS) W $00C
13 Timer mode register C1 (TMC1) W $00D
14 Timer C
(TRCL/TWCL) R/W $00E
15
(TRCU/TWCU) R/W $00F
16 Timer mode register D1 (TMD1) W $010
17 Timer D
(TRDL/TWDL) R/W $011
18
(TRDU/TWDU) R/W $012
19 Timer mode register B2 (TMB2) R/W $013
20 Timer mode register C2 (TMC2) R/W $014
21 Timer mode register D2 (TMD2) R/W $015
22 A/D data register
(AMR) W $016
23 A/D data register lower (ADRL) R $017
24 A/D data register upper (ADRU) R $018
25
26
Not used
$019
$01A
27 Serial mode register 2A (SM2A) W $01B
28 Serial mode register 2B (SM2B) W $01C
29 Serial data register 2 lower (SR2L) R/W $01D
30 Serial data register 2 upper (SR2U) R/W $01E
31
Not used
$01F
32
Register flag area
35
$020
$023
36 Port mode register B
(PMRB) W $024
37 Port mode register C (PMRC) W $025
38 Detection edge select register 1 (ESR1) W $026
39 Detection edge select register 2 (ESR2) W $027
40 Serial mode register 1B (SM1B) W $028
41 System clock select register (SSR) W $029
42
Not used
43
$02A
$02B
44 Port D₀ –D₃DCR
(DCD0) _W
45 Port D₄ –D₇DCR
(DCD1) W
46 Port D₈ and D₁₁ DCR (DCD2) W
47
Not used
$02C
$02D
$02E
$02F
48 Port R0 DCR
(DCR0) W $030
49 Port R1 DCR
(DCR1) W $031
50 Port R2 DCR
(DCR2) W $032
51 Port R3 DCR
(DCR3) W $033
52 Port R4 DCR
(DCR4) W $034
53 Port R5 DCR
(DCR5) W $035
54 Port R6 DCR
(DCR6) W $036
55 Port R7 DCR
(DCR7) W $037
56 Port R8 DCR
(DCR8) W $038
57 Port R9 DCR
(DCR9) W $039
58 Port RA DCR
(DCRA) W $03A
59 Port RB DCR
(DCRB) W $03B
60 Port RC DCR
(DCRC) W $03C
Not used
63 V register
R/W $03F
10 Timer read register B lower (TRBL) R Timer write register B lower (TWBL) W $00A
11 Timer read register B upper (TRBU) R Timer write register B upper (TWBU) W $00B
14 Timer read register C lower (TRCL) R Timer write register C lower (TWCL) W $00E
15 Timer read register C upper (TRCU) R Timer write register C upper (TWCU) W $00F
17 Timer read register D lower (TRDL) R ^{Timer write register D lower} (TWDL) W $011
18 Timer read register D upper (TRDU) R Timer write register D upper (TWDU) W $012
Figure 2 RAM Memory Map
7