H838799 Datasheet, PDF (87/686 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer

Section 3 Exception Handling
Section 3 Exception Handling
Exception handling may be caused by a reset or interrupts.
• Reset
A reset has the highest exception priority. Exception handling starts as soon as the reset is
cleared by the RES pin. The chip is also reset when the watchdog timer overflows, and
exception handling starts. Exception handling is the same as exception handling by the RES
pin.
• Interrupts
External interrupts other than NMI and internal interrupts other than address break are masked
by the I bit in CCR, and kept masked while the I bit is set to 1. Exception handling starts when
the current instruction or exception handling ends, if an interrupt request has been issued.
Rev. 1.00 Jul. 11, 2007 Page 49 of 644
REJ09B0380-0100