H838799 Datasheet, PDF (112/686 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer

Section 4 Interrupt Controller
When exception handling for the WKP7 to WKP0 interrupts is accepted, the I bit in CCR is set to
1. The interrupt mask level can be set by IPR.
(3) IRQ4, IRQ3, IRQ1, and IRQ0 Interrupts
IRQ4, IRQ3, IRQ1, and IRQ0 interrupts are requested by input signals at IRQ4, IRQ3, IRQ1, and
IRQ0 pins.
Using the IEG4, IEG3, IEG1, and IEG0 bits in IEGR, it is possible to select whether an interrupt
is generated by a rising or falling edge at IRQ4, IRQ3, IRQ1, and IRQ0 pins.
When the specified edge is input while the IRQ4, IRQ3, IRQ1, and IRQ0 pin functions are
selected by PFCR, PMRF, PMRE, PMRB, and PMR9, the corresponding bit in IRR1 is set to 1
and an interrupt request is generated.
Clearing the IEN4, IEN3, IEN1, and IEN0 bits in IENR1 to 0 disables the interrupt request to be
accepted. Setting the I bit in CCR to 1 masks all interrupts.
The interrupt mask level can be set by IPR.
(4) IRQAEC Interrupts
An IRQAEC interrupt is requested by an input signal at the IRQAEC pin or IECPWM (PWM
output for the AEC). When the IRQAEC pin is used as an external interrupt pin, clear the
ECPWME bit in AEGSR to 0.
Using the AIEGS1 and AIEGS0 bits in AEGSR, it is possible to select whether an interrupt is
generated by a rising edge, falling edge, or both edges.
When the IENEC2 bit in IENR1 is set to 1 and the specified edge is input, the corresponding bit in
IRR1 is set to 1 and an interrupt request is generated.
When exception handling for the IRQAEC interrupt is accepted, the I bit in CCR is set to 1.
The interrupt mask level can be set by IPR.
Rev. 1.00 Jul. 11, 2007 Page 74 of 644
REJ09B0380-0100