H838799 Datasheet, PDF (278/686 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer

Section 12 Timer F
Bit
2
1
0
Note:
Initial
Bit Name Value R/W Description
CKSL2
0
W
Clock Select L
CKSL1
0
CKSL0
0
W
Select the clock input to TCFL from among four internal
W
clock sources or external event input.
000: Counting on a rising or falling edge of an external
event (on the TMIF pin)*
001: Counting on a rising or falling edge of an external
event (on the TMIF pin)*
010: Counting on a rising or falling edge of an external
event (on the TMIF pin)*
011: Using prohibited
100: Internal clock: counting on φ/32
101: Internal clock: counting on φ/16
110: Internal clock: counting on φ/4
111: Internal clock: counting on φ_W/4
* The TMIFEG bit in IEGR selects which edge of an external event is used for counting.
12.3.4 Timer Control/Status Register F (TCSRF)
TCSRF performs counter clear selection, overflow flag setting, and compare match flag setting,
and controls enabling of overflow interrupt requests.
Initial
Bit
Bit Name Value R/W Description
7
OVFH
0
R/(W)* Timer Overflow Flag H
[Setting condition]
TCFH overflows from H'FF to H'00
[Clearing condition]
Writing of 0 to bit OVFH after reading OVFH = 1
6
CMFH
0
R/(W)* Compare Match Flag H
This is a status flag indicating that TCFH has matched
OCRFH.
[Setting condition]
The TCFH value matches the OCRFH value
[Clearing condition]
Writing of 0 to bit CMFH after reading CMFH = 1
Rev. 1.00 Jul. 11, 2007 Page 240 of 644
REJ09B0380-0100