H838799 Datasheet, PDF (25/686 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer

Figures
Section 1 Overview
Figure 1.1 Internal Block Diagram of H8/38799 Group................................................................. 3
Figure 1.2 Pin Assignment of H8/38799 Group (PLQP0100KB-A) .............................................. 4
Section 2 CPU
Figure 2.1 Memory Map............................................................................................................... 13
Figure 2.2 CPU Registers ............................................................................................................. 14
Figure 2.3 Usage of General Registers ......................................................................................... 15
Figure 2.4 Relationship between Stack Pointer and Stack Area ................................................... 16
Figure 2.5 General Register Data Formats (1) .............................................................................. 18
Figure 2.5 General Register Data Formats (2) .............................................................................. 19
Figure 2.6 Memory Data Formats................................................................................................. 20
Figure 2.7 Instruction Formats...................................................................................................... 31
Figure 2.8 Branch Address Specification in Memory Indirect Mode ........................................... 35
Figure 2.9 On-Chip Memory Access Cycle.................................................................................. 38
Figure 2.10 On-Chip Peripheral Module Access Cycle (3-State Access)..................................... 39
Figure 2.11 CPU Operating States................................................................................................ 40
Figure 2.12 State Transitions ........................................................................................................ 41
Figure 2.13 Example of Timer Configuration with Two Registers Allocated to
Same Address............................................................................................................ 42
Section 3 Exception Handling
Figure 3.1 Reset Exception Handling Sequence ........................................................................... 52
Figure 3.2 Interrupt Sources and their Numbers........................................................................... 53
Figure 3.3 Stack Status after Exception Handling ........................................................................ 54
Figure 3.4 Operation when Odd Address is Set in SP .................................................................. 55
Figure 3.5 Port Mode Register (or AEGSR) Setting and Interrupt Request Flag Clearing
Procedure .................................................................................................................... 58
Section 4 Interrupt Controller
Figure 4.1 Block Diagram of Interrupt Controller ........................................................................ 61
Figure 4.2 Flowchart of Procedure Up to Interrupt Acceptance ................................................... 81
Figure 4.3 Interrupt Exception Handling Sequence...................................................................... 82
Figure 4.4 Contention between Interrupt Generation and Disabling ............................................ 84
Section 5 Clock Pulse Generator
Figure 5.1 Block Diagram of Clock Pulse Generator ................................................................... 87
Figure 5.2 Typical Connection to Crystal Resonator.................................................................... 90
Figure 5.3 Typical Connection to Ceramic Resonator.................................................................. 91
Rev. 1.00 Jul. 11, 2007 Page xxv of xxxviii