HD404849 Datasheet, PDF (85/127 Pages) Hitachi Semiconductor – 4-Bit Single-Chip Microcomputer

HD404849 Series
External clock mode
STS wait state
(Octal counter = 000,
transmit clock disabled)
00 MCU reset
SMRA write 04
01 STS instruction
06 SMRA write (IFS ^← 1)
Transmit clock wait state
(Octal counter = 000)
02 Transmit clock
03
8 transmit clocks
05
STS instruction (IFS ^← 1)
Transfer state
(Octal counter = 000)
Internal clock mode
SMRA write
18
STS wait state
(Octal counter = 000,
transmit clock disabled)
10 MCU reset
Clock continuous output state
(PMRA 0, 1 = 00)
SMRA write 14
11 STS instruction
Transmit clock 17
Transmit clock wait state
(Octal counter = 000)
12 Transmit clock
15
STS instruction (IFS ← 1)
13 8 transmit clocks
16 SMRA write (IFS ←1)
Transfer state
(Octal counter = 000)
Note: Refer to the Operating States section for the corresponding encircled numbers.
Figure 67 Serial Interface State Transitions
Output Level Control in Idle States: In idle states, that is, STS wait state and transmit clock wait state,
the output level of the SO pin can be controlled by setting bit 1 (SMRB1) of serial mode register B (SMRB:
$028) to 0 or 1. The output level control example is shown in figure 68. Note that the output level cannot
be controlled in transfer state.
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