R1LV0216BSB Datasheet, PDF (8/16 Pages) Renesas Technology Corp – 2Mb Advanced LPSRAM (128k word x 16bit)

R1LV0216BSB
Write Cycle
Parameter
Write cycle time
Address valid to end of write
Chip select to end of write
Write pulse width
LB#, UB# valid to end of write
Address setup time
Write recovery time
Data to write time overlap
Data hold from write time
Output enable from end of write
Output disable to output in high-Z
Write to output in high-Z
Symbol
t_WC
t_AW
t_CW
t_WP
t_BW
t_AS
t_WR
t_DW
t_DH
t_OW
t_OHZ
t_WHZ
R1LV0216BSB-5S*
Min.
Max.
55
-
50
-
50
-
45
-
50
-
0
-
0
-
25
-
0
-
5
-
0
20
0
20
R1LV0216BSB-7S*
Min.
Max.
70
-
55
-
55
-
50
-
55
-
0
-
0
-
30
-
0
-
5
-
0
25
0
25
Unit Note
ns
ns
ns
5
ns
4
ns
ns
6
ns
7
ns
ns
ns
2
ns
1,2
ns
1,2
Note
1. t_CHZ, t_OHZ and t_WHZ are defined as the time at which the outputs achieve the open circuit conditions and are not
referred to output voltage levels.
2. This parameter is sampled and not 100% tested.
3. At any given temperature and voltage condition, t_HZ max is less than t_LZ min both for a given device and from
device to device.
4. A write occurs during the overlap of a low CS#, a low WE# and a low LB# or a low UB#.
A write begins at the latest transition among CS# going low, WE# going low and LB# going low or UB# going
low.
A write ends at the earliest transition among CS# going high, WE# going high and LB# going high or UB#
going high.
t_WP is measured from the beginning of write to the end of write.
5. t_CW is measured from the later of CS# going low to end of write.
6. t_AS is measured the address valid to the beginning of write.
7. t_WR is measured from the earliest of CS#, WE#, LB# or UB# going high to the end of write cycle.
8. Don’t apply inverted phase signal externally when DQ pin is output mode.
R10DS0051EJ0100 Rev.1.00
2011.03.30
Page 8 of 14