R1LV0216BSB Datasheet, PDF (13/16 Pages) Renesas Technology Corp – 2Mb Advanced LPSRAM (128k word x 16bit)

R1LV0216BSB
Low Vcc Data Retention Characteristics
Parameter
V_CC for data retention
Symbol Min. Typ. Max. Unit
Test conditions^*2
Vin ≥ 0V
V_DR
2.0
-
3.6
V ^{(1) CS# ≥ Vcc-0.2V or}
(2) LB# = UB# ≥ Vcc-0.2V,
CS# ≤ 0.2V
-
1^*1
2
μA ~+25°C
Vcc=3.0V, Vin ≥ 0V
Data retention current
-
-
3
μA ~+40°C
(1) CS# ≥ Vcc-0.2V or
I_CCDR
(2) LB# = UB# ≥ Vcc-0.2V,
-
-
8
μA ~+70°C
CS# ≤ 0.2V
-
-
10 μA ~+85°C
Chip deselect to data retention time t_CDR
0
-
-
ns
See retention waveform.
Operation recovery time
t_R
5
-
-
ms
Note 1. Typical parameter indicates the value for the center of distribution at 3.0V (Ta= 25ºC), and not 100% tested.
2. CS# controls address buffer, WE# buffer, OE# buffer, LB# buffer, UB# buffer and Din buffer. If CS# controls
data retention mode, Vin levels (address, WE#, OE#, LB#, UB#, DQ) can be in the high impedance state.
R10DS0051EJ0100 Rev.1.00
2011.03.30
Page 13 of 14