H8S-2345 Datasheet, PDF (783/927 Pages) Renesas Technology Corp – 16-Bit Single-Chip Microcomputer

Appendix B Internal I/O Register
Address Register
(low) Name Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Module
Name
Data Bus
Width
H'FFDC TGR0C
TPU1
16 bit
H'FFDD
H'FFDE TGR0D
H'FFDF
H'FFE0 TCR1 —
CCLR1 CCLR0 CKEG1 CKEG0 TPSC2 TPSC1 TPSC0
H'FFE1 TMDR1 —
—
—
—
MD3 MD2 MD1 MD0
H'FFE2 TIOR1 IOB3 IOB2 IOB1 IOB0 IOA3 IOA2 IOA1 IOA0
H'FFE4 TIER1 TTGE —
TCIEU TCIEV —
—
TGIEB TGIEA
H'FFE5 TSR1 TCFD —
TCFU TCFV —
—
TGFB TGFA
H'FFE6 TCNT1
H'FFE7
H'FFE8 TGR1A
H'FFE9
H'FFEA TGR1B
H'FFEB
H'FFF0 TCR2 —
CCLR1 CCLR0 CKEG1 CKEG0 TPSC2 TPSC1 TPSC0 TPU2
16 bit
H'FFF1 TMDR2 —
—
—
—
MD3 MD2 MD1 MD0
H'FFF2 TIOR2 IOB3 IOB2 IOB1 IOB0 IOA3 IOA2 IOA1 IOA0
H'FFF4 TIER2 TTGE —
TCIEU TCIEV —
—
TGIEB TGIEA
H'FFF5 TSR2 TCFD —
TCFU TCFV —
—
TGFB TGFA
H'FFF6 TCNT2
H'FFF7
H'FFF8 TGR2A
H'FFF9
H'FFFA TGR2B
H'FFFB
Notes: 1. Located in on-chip RAM. The bus width is 32 bits when the DTC accesses this area as
register information, and 16 bits otherwise.
2. Functions as C/A for SCI use, and as GM for smart card interface use.
3. Functions as FER for SCI use, and as ERS for smart card interface use.
Rev. 4.00 Feb 15, 2006 page 759 of 900
REJ09B0291-0400