H8S-2345 Datasheet, PDF (169/927 Pages) Renesas Technology Corp – 16-Bit Single-Chip Microcomputer

Section 6 Bus Controller
6.3.6 Chip Select Signals
The H8S/2345 Group can output chip select signals (CS0 to CS3) to areas 0 to 3, the signal being
driven low when the corresponding external space area is accessed. In normal mode*, only the
CS0 signal can be output.
Figure 6.3 shows an example of CSn (n = 0 to 3) output timing.
Enabling or disabling of the CSn signal is performed by setting the data direction register (DDR)
for the port corresponding to the particular CSn pin.
In ROM-disabled expansion mode, the CS0 pin is placed in the output state after a power-on reset.
Pins CS1 to CS3 are placed in the input state after a power-on reset, and so the corresponding
DDR should be set to 1 when outputting signals CS1 to CS3.
In ROM-enabled expansion mode, pins CS0 to CS3 are all placed in the input state after a power-
on reset, and so the corresponding DDR should be set to 1 when outputting signals CS0 to CS3.
For details, see section 8, I/O Ports.
Note: * ZTAT, mask ROM, and ROMless versions only.
Bus cycle
T₁
T₂
T₃
φ
Address bus
Area n external address
CSn
Figure 6.3 CSn Signal Output Timing (n = 0 to 3)
Rev. 4.00 Feb 15, 2006 page 145 of 900
REJ09B0291-0400