H8S-2345 Datasheet, PDF (423/927 Pages) Renesas Technology Corp – 16-Bit Single-Chip Microcomputer

11.2.2 Timer Control/Status Register (TCSR)
Bit
:
7
6
5
4
OVF WT/IT TME
—
Initial value :
0
0
0
1
R/W
: R/(W)^* R/W R/W
—
Section 11 Watchdog Timer
3
2
1
0
—
CKS2 CKS1 CKS0
1
0
0
0
—
R/W
R/W
R/W
Note: * Can only be written with 0 for flag clearing.
TCSR is an 8-bit readable/writable* register. Its functions include selecting the clock source to be
input to TCNT, and the timer mode.
TCR is initialized to H'18 by a reset and in hardware standby mode. It is not initialized in software
standby mode.
Note: * The method for writing to TCSR is different from that for general registers to prevent
inadvertent overwriting. For details see section 11.2.4, Notes on Register Access.
Bit 7—Overflow Flag (OVF): Indicates that TCNT has overflowed from H'FF to H'00, when in
interval timer mode. This flag cannot be set during watchdog timer operation.
Bit 7
OVF
Description
0
[Clearing condition]
Cleared by reading TCSR when OVF = 1^*, then writing 0 to OVF
(Initial value)
1
[Setting condition]
Set when TCNT overflows (changes from H'FF to H'00) in interval timer mode
Note: * When OVF is polled and the interval timer interrupt is disabled. OVF = 1 must be read
at least twice.
Bit 6—Timer Mode Select (WT/IT): Selects whether the WDT is used as a watchdog timer or
interval timer. If used as an interval timer, the WDT generates an interval timer interrupt request
(WOVI) when TCNT overflows. If used as a watchdog timer, the WDT generates the WDTOVF
signal* when TCNT overflows.
Note: * The WDTOVF pin function is not supported by the F-ZTAT version.
Rev. 4.00 Feb 15, 2006 page 399 of 900
REJ09B0291-0400