H8S-2345 Datasheet, PDF (152/927 Pages) Renesas Technology Corp – 16-Bit Single-Chip Microcomputer

Section 5 Interrupt Controller
(2) Determination of Priority
The DTC activation source is selected in accordance with the default priority order, and is not
affected by mask or priority levels. See section 7.3.3, DTC Vector Table, for the respective
priorities.
(3) Operation Order
If the same interrupt is selected as a DTC activation source and a CPU interrupt source, the DTC
data transfer is performed first, followed by CPU interrupt exception handling.
If the same interrupt is selected as a DTC activation source or CPU interrupt source, operations are
performed for them independently according to their respective operating statuses and bus
mastership priorities.
Table 5.11 summarizes interrupt source selection and interrupt source clearance control according
to the settings of the DTCE bit of DTCEA to DTCEE in the DTC and the DISEL bit of MRB in
the DTC.
Table 5.11 Interrupt Source Selection and Clearing Control
Settings
DTC
Interrupt Source Selection/Clearing Control
DTCE
DISEL
DTC
CPU
0
*
X
∆
1
0
∆
X
1
∆
Legend:
∆ : The relevant interrupt is used. Interrupt source clearing is performed.
(The CPU should clear the source flag in the interrupt handling routine.)
: The relevant interrupt is used. The interrupt source is not cleared.
X : The relevant bit cannot be used.
* : Don't care
(4) Notes on Use
SCI and A/D converter interrupt sources are cleared when the DTC reads or writes to the
prescribed register, and are not dependent upon the DISEL bit.
Rev. 4.00 Feb 15, 2006 page 128 of 900
REJ09B0291-0400