M306V8FJFP Datasheet, PDF (77/365 Pages) Renesas Technology Corp – SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

M306V8FJFP
Interrupt Sequence
An interrupt sequence — what are performed over a period from the instant an interrupt is accepted to the
instant the interrupt routine is executed — is described here.
If an interrupt occurs during execution of an instruction, the processor determines its priority when the
execution of the instruction is completed, and transfers control to the interrupt sequence from the next
cycle. If an interrupt occurs during execution of either the SMOVB, SMOVF, SSTR or RMPA instruction,
the processor temporarily suspends the instruction being executed, and transfers control to the interrupt
sequence.
The CPU behavior during the interrupt sequence is described below. Figure 7.5 shows time required for
executing the interrupt sequence.
(1) The CPU gets interrupt information (interrupt number and interrupt request priority level) by reading the
address 0000016. Then it clears the IR bit for the corresponding interrupt to “0” (interrupt not re-
quested).
(2) The FLG register immediately before entering the interrupt sequence is saved to the CPU’s internal
temporary register^{(Note 1)}.
(3) The I, D and U flags in the FLG register become as follows:
The I flag is cleared to “0” (interrupts disabled).
The D flag is cleared to “0” (single-step interrupt disabled).
The U flag is cleared to “0” (ISP selected).
However, the U flag does not change state if an INT instruction for software interrupt Nos. 32 to 63 is
executed.
(4) The CPU’s internal temporary register ^{(Note 1)} is saved to the stack.
(5) The PC is saved to the stack.
(6) The interrupt priority level of the accepted interrupt is set in the IPL.
(7) The start address of the relevant interrupt routine set in the interrupt vector is stored in the PC.
After the interrupt sequence is completed, the processor resumes executing instructions from the start
address of the interrupt routine.
Note: This register cannot be used by user.
CPU clock
Address bus
Data bus
RD
WR
(Note 2)
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18
Address
000016
Indeterminate (Note 1)
SP-2
SP-4
vec
vec+2
PC
Interrupt
information
Indeterminate (Note 1)
SP-2
SP-4
vec
vec+2
contents contents contents contents
Indeterminate (Note 1)
Note 1 : The indeterminate state depends on the instruction queue buffer. A read cycle occurs when
the instruction queue buffer is ready to accept instructions.
Note 2 : The WR signal timing shown here is for the case where the stack is located in the internal RAM.
Figure 7.5. Time Required for Executing Interrupt Sequence
Rev.1.31 Apr 18, 2005 page 77 of 363
REJ03B0082-0131