PD17012GF-058_15 Datasheet, PDF (75/94 Pages) Renesas Technology Corp – PLL FREQUENCY SYNTHESIZER AND CONTROLLER FOR FM/MW/LW TUNER (AUTOMOBILE APPLICATION)

7. MUTE OUTPUT TIMING CHARTS
The numbers <1> through <6> in this chapter represent the following:
<1>: Key-on chattering protection
<2>: Preceding mute and beep output
<3>: Updating of the frequency division ratio setting and indication
<4>: Following mute
<5>: Scan time
<6>: Wait for PLL locking
7.1 Radio Mute (RDMUTE Pin) Output Timing Charts
(1) Manual up/down
(a) 1-channel up/down
(i) When AUTO500 switch = 0
<1> <2> <3>
<4>
15 ms 40 ms
200 - 300 ms
µPD17012GF-058
Key on
(ii) When AUTO500 switch = 1
<1>
<2> <3>
<4>
0.5 second
15 ms _{or less} 40 ms
200 - 300 ms
Key on
Key off
In either case (i) or case (ii), the time of <4> is 600 ms to 700 ms at the band edges (lowest frequency
←→ ^{highest frequency).}
73