7702 Datasheet, PDF (72/522 Pages) Renesas Technology Corp – 16-BIT SINGLE-CHIP MICROCOMPUTER

INTERRUPTS
4.4 Interrupt priority level
4.4 Interrupt priority level
When two or more interrupt requests are detected at the same sampling timing, at which whether an
interrupt request exists or not is checked, in the case of the interrupt disable flag (I) = “0” (interrupts
enabled); they are accepted in order of priority levels, with the highest priority interrupt request accepted
first.
Among a total of 19 interrupt sources, the user can set the desired priority levels for 16 interrupt sources
except software interrupts (zero division and BRK instruction interrupts) and the watchdog timer interrupt.
Use the interrupt priority level select bits to set their priority levels. Additionally, the reset, which is handled
as one that has the highest priority of all interrupts, and the watchdog timer interrupt have their priority levels
set by hardware. Figure 4.4.1 shows the interrupt priority levels set by hardware.
Note that software interrupts are not affected by interrupt priority levels. Whenever the instruction is executed,
a branch is certain to be made to the interrupt routine.
Reset
Watchdog
timer
••••••••••••••••••
Priority levels determined by hardware
16 interrupt sources except software interrupts
and watchdog timer interrupt
The user can set the desired priority levels inside of the dotted line.
Low
Priority level
High
Fig. 4.4.1 Interrupt priority levels set by hardware
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7702/7703 Group User’s Manual