7702 Datasheet, PDF (176/522 Pages) Renesas Technology Corp – 16-BIT SINGLE-CHIP MICROCOMPUTER

SERIAL I/O
7.2 Block description
The UARTi receive register is used to convert serial data which is input to the RxDi pin into parallel data.
This register takes in the input signal to the RxDi pin synchronously with the transfer clock, one bit at a
time.
The UARTi receive buffer register is used to read out receive data. When reception is completed, receive
data which is taken in the UARTi receive register is automatically transferred to the UARTi receive buffer
register. The contents of UARTi receive buffer register is updated when the next data is ready before
reading out the data which has been transferred to the UARTi receive buffer register (i.e., an overrun error
occurs).
The UARTi receive buffer register is initialized by setting the receive enable bit (bit 2 at addresses 3516,
3D16) to “1” after clearing it to “0.”
Figure 7.2.9 shows the contents of UARTi receive buffer register when reception is completed.
In UART mode
(Transfer data length : 9 bits)
In clock synchronous
serial I/O mode
In UART mode
(Transfer data length : 8 bits)
In UART mode
(Transfer data length : 7 bits)
High-order byte
(addresses 3716, 3F16)
Low-order byte
(addresses 3616, 3E16)
b7
b0 b7
b0
0 000000
Receive data (9 bits)
0 000000
Same value as bit
7 in low-order byte
0 000000
Same value as bit
6 in low-order byte
Receive data (8 bits)
Receive data (7 bits)
Fig. 7.2.9 Contents of UARTi receive buffer register when reception is completed
7–12
7702/7703 Group User’s Manual