H8S2678 Datasheet, PDF (705/979 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2600 Series

TCNT count
H'FF
Section 14 Watchdog Timer
Overflow
H'00
WT/IT=1
TME=1
H'00 written
to TCNT
WDTOVF signal
Internal reset signal^*1
WOVF=1
WDTOVF and
internal reset are
generated
Time
WT/IT=1 H'00 written
TME=1 to TCNT
132 states^*2
Legend:
WT/IT : Timer mode select bit
TME : Timer enable bit
518 states
Notes: 1. If TCNT overflows when the RSTE bit is set to 1, an internal reset signal is generated.
2. 130 states when the RSTE bit is cleared to 0.
Figure 14.2 Operation in Watchdog Timer Mode
14.4.2 Interval Timer Mode
To use the WDT as an interval timer, set the WT/IT bit to 0 and TME bit in TCSR to 1.
When the WDT is used as an interval timer, an interval timer interrupt (WOVI) is generated each
time the TCNT overflows. Therefore, an interrupt can be generated at intervals.
When the TCNT overflows in interval timer mode, an interval timer interrupt (WOVI) is requested
at the same time the OVF bit in the TCSR is set to 1.
Rev. 3.00 Mar 17, 2006 page 655 of 926
REJ09B0283-0300