H8S2678 Datasheet, PDF (180/979 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2600 Series

Section 6 Bus Controller (BSC)
Bit Bit Name Initial Value R/W
Description
10
W22
1
9
W21
1
8
W20
1
R/W
Area 2 Wait Control 2 to 0
R/W
These bits select the number of program wait
R/W
states when accessing area 2 while AST2 bit in
ASTCR = 1.
A CAS latency is set when the synchronous
DRAM is connected^*. The setting of area 2 is
reflected to the setting of areas 2 to 5. A CAS
latency can be set regardless of whether or not
an ASTCR wait state insertion is enabled.
000: Program wait not inserted
001: 1 program wait state inserted
010: 2 program wait states inserted
011: 3 program wait states inserted
100: 4 program wait states inserted
101: 5 program wait states inserted
110: 6 program wait states inserted
111: 7 program wait states inserted
000: Synchronous DRAM of CAS latency 1 is
connected to areas 2 to 5.
001: Synchronous DRAM of CAS latency 2 is
connected to areas 2 to 5.
010: Synchronous DRAM of CAS latency 3 is
connected to areas 2 to 5.
011: Synchronous DRAM of CAS latency 4 is
connected to areas 2 to 5.
1XXX: Setting prohibited.
Note: * The synchronous DRAM interface is not supported in the H8S/2678 Group.
Legend: x: Don’t care.
Rev. 3.00 Mar 17, 2006 page 130 of 926
REJ09B0283-0300