H8S2678 Datasheet, PDF (417/979 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2600 Series

Section 8 EXDMA Controller
φ
Address bus
Channel 0 transfer
Channel 1 transfer
Channel 2 transfer
Channel 0
Bus
release
Channel 1
Bus
release
Channel 2
EXDMA control
Idle
Channel 0
Channel 1
Channel 2
Channel 0
Request cleared
Channel 1
Channel 2
Request Selected Request cleared
held
Request Not Request
held ^selected held
Selected Request cleared
Figure 8.13 Example of Channel Priority Timing
Transfer Requests from Multiple Channels in Auto Request Cycle Steal Mode: If transfer
requests for different channels are issued during a transfer in auto request cycle steal mode, the
operation depends on the channel priority. If the channel that made the transfer request is of higher
priority than the channel currently performing transfer, the channel that made the transfer request
is selected.
If the channel that made the transfer request is of lower priority than the channel currently
performing transfer, that channel’s transfer request is held pending, and the currently transferring
channel remains selected.
The selected channel begins transfer after the currently transferring channel releases the bus. If
there is a bus request from a bus mastership other than the EXDMAC at this time, a cycle for the
other bus mastership is initiated. If there is no other bus request, the bus is released for one cycle.
Figure 8.14 shows examples of transfer timing in cases that include auto request cycle steal mode.
Rev. 3.00 Mar 17, 2006 page 367 of 926
REJ09B0283-0300