H8S2678 Datasheet, PDF (20/979 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2600 Series

9.5.3 Block Transfer Mode ........................................................................................... 414
9.5.4 Chain Transfer ..................................................................................................... 415
9.5.5 Interrupt Sources.................................................................................................. 416
9.5.6 Operation Timing................................................................................................. 417
9.5.7 Number of DTC Execution States........................................................................ 418
9.6 Procedures for Using DTC................................................................................................ 420
9.6.1 Activation by Interrupt......................................................................................... 420
9.6.2 Activation by Software ........................................................................................ 420
9.7 Examples of Use of the DTC ............................................................................................ 421
9.7.1 Normal Mode....................................................................................................... 421
9.7.2 Chain Transfer ..................................................................................................... 422
9.7.3 Chain Transfer when Counter = 0........................................................................ 423
9.7.4 Software Activation ............................................................................................. 425
9.8 Usage Notes ...................................................................................................................... 426
9.8.1 Module Stop Mode Setting .................................................................................. 426
9.8.2 On-Chip RAM ..................................................................................................... 426
9.8.3 DTCE Bit Setting................................................................................................. 426
Section 10 I/O Ports ............................................................................................................ 427
10.1 Port 1................................................................................................................................. 432
10.1.1 Port 1 Data Direction Register (P1DDR)............................................................. 432
10.1.2 Port 1 Data Register (P1DR)................................................................................ 433
10.1.3 Port 1 Register (PORT1)...................................................................................... 433
10.1.4 Pin Functions ....................................................................................................... 434
10.2 Port 2................................................................................................................................. 443
10.2.1 Port 2 Data Direction Register (P2DDR)............................................................. 443
10.2.2 Port 2 Data Register (P2DR)................................................................................ 444
10.2.3 Port 2 Register (PORT2)...................................................................................... 444
10.2.4 Pin Functions ....................................................................................................... 445
10.3 Port 3................................................................................................................................. 454
10.3.1 Port 3 Data Direction Register (P3DDR)............................................................. 454
10.3.2 Port 3 Data Register (P3DR)................................................................................ 455
10.3.3 Port 3 Register (PORT3)...................................................................................... 455
10.3.4 Port 3 Open Drain Control Register (P3ODR)..................................................... 456
10.3.5 Port Function Control Register 2 (PFCR2) .......................................................... 457
10.3.6 Pin Functions ....................................................................................................... 458
10.4 Port 4................................................................................................................................. 461
10.4.1 Port 4 Register (PORT4)...................................................................................... 461
10.4.2 Pin Functions ....................................................................................................... 461
10.5 Port 5................................................................................................................................. 462
10.5.1 Port 5 Data Direction Register (P5DDR)............................................................. 463
Rev. 3.00 Mar 17, 2006 page xx of l