PD16721_15 Datasheet, PDF (7/30 Pages) Renesas Technology Corp – 384-OUTPUT TFT-LCD SOURCE DRIVER (COMPATIBLE WITH 256-GRAY SCALES)

µPD16721
(2/2)
Pin Symbol
Pin Name
I/O
Description
MODE
POL21,
POL22
VSEL
V0 to V15
5
TEST
5 VDD1
VDD2
VSS1
VSS2
Output reset control
I
MODE = H or open: Output reset
MODE = L: No output reset
MODE is pulled up to the VDD1 in the LSI.
Data inversion
I
Select of inversion or no inversion for input data.
POL21: Data inversion or no inversion of Port1.
POL22: Data inversion or no inversion of Port2
POL21/22 = H: Data are inverted in the LSI.
POL21/22 = L: Data are not inverted in the LSI.
Driver voltage select
I
The driver voltage can be switched by controlling the stationary bias
current of the output amplifier via VSEL.
VSEL = H: VDD2 = 13.0 V (large bias current)
VSEL = L or open: VDD2 = 15.0 V (small bias current)
LPC is pulled down to the VSS1 in the LSI.
γ -corrected power supplies
−
Input the γ -corrected power supplies from outside by using operational
amplifier. During the gray scale voltage output, be sure to keep the gray
scale level power supply at a constant level. Make sure to maintain the
following relationships.
VDD2–0.2 V ≥ V0 > V1 > V2 > ....... > V6 > V7 ≥ 0.5 VDD2 + 0.5 V
0.5 VDD2–0.5 V ≥ V8 > V9 > V10 > ....... V14 > V15 ≥ VSS2 + 0.2 V
Test
I
Normally, set the TEST pin to high level or leave open.
This pin is pulled up to VDD1 in the LSI.
Logic power supply
−
2.5 to 3.4 V
Driver power supply
−
13.0 ± 0.5 V or 15.0 ± 0.5 V
Logic ground
−
Grounding
Driver ground
−
Grounding
Cautions 1. The power start sequence must be VDD1, logic input, and VDD2 & V0 to V15 in that order.
Reverse this sequence to shut down.
2. To stabilize the supply voltage, please be sure to insert a 0.47 µF bypass capacitor between
VDD1 to VSS1 and VDD2 to VSS2. Furthermore, for increased precision of the D/A converter,
insertion of a bypass capacitor of about 0.1 µF is also advised between the γ-corrected
power supply terminals (V0, V1, V2,....., V15) and VSS2.
DataSheet S14791EJ1V0DS
5