PD16721_15 Datasheet, PDF (23/30 Pages) Renesas Technology Corp – 384-OUTPUT TFT-LCD SOURCE DRIVER (COMPATIBLE WITH 256-GRAY SCALES)

µPD16721
5 Timing Requirements (TA = _−10 to +75°C, VDD1 = 2.5 to 3.4 V, VSS1 = 0 V, tr = tf = 5.0 ns)
Parameter
Symbol
Condition
MIN.
TYP.
5 Clock pulse width
PWCLK 2.5 V ≤ VDD1 ≤ 3.0 V
18
3.0 V ≤ VDD1 ≤ 3.4 V
14
5 Clock pulse high period
PWCLK (H) 2.5 V ≤ VDD1 ≤ 3.0 V
6
3.0 V ≤ VDD1 ≤ 3.4 V
4
Clock pulse low period
PWCLK (L)
4
Data setup time
tSETUP1
0
Data hold time
tHOLD1
4
Start pulse setup time
tSETUP2
0
Start pulse hold time
tHOLD2
4
POL21/22 setup time
tSETUP3
0
POL21/22 hold time
tHOLD3
4
5 STB pulse width
PWSTB
1.0
Last data timing
tLDT
2
CLK-STB time
tCLK-STB CLK ↑→ STB↑
4
STB-CLK time
tSTB-CLK STB ↑→ CLK↑
4
Time between STB and start pulse tSTB-STH STB ↑→ STHR (STHL) ↑
2
POL-STB time
tPOL-STB POL ↑ or ↓→ STB ↑
4
STB-POL time
tSTB-POL STB ↓→ POL ↓ or ↑
4
STB-SRC time
t STB-SRC STB ↑ → SRC ↑
0
STB-ORC time
tSTB-ORC STB ↓→ ORC ↑
0
5 Remark Unless otherwise specified, the input level is defined to be VIH = 0.7 VDD1, VIL = 0.3 VDD1.
MAX.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
CLK
ns
ns
CLK
ns
ns
ns
ns
DataSheet S14791EJ1V0DS
21