PD16721_15 Datasheet, PDF (18/30 Pages) Renesas Technology Corp – 384-OUTPUT TFT-LCD SOURCE DRIVER (COMPATIBLE WITH 256-GRAY SCALES)

µPD16721
7. RELATIONSHIP BETWEEN MODE, STB, SRC, ORC, POL, AND OUTPUT WAVEFORM
When the MODE pin is high level or left open and STB is high level, all outputs are reset (shorted) and the gray-
scale voltage is output to LCD in synchronization with the falling edge of STB.
When the MODE pin is low level and STB is high level, all outputs became Hi-Z and the gray-scale voltage is output
to the LCD in synchronization with the falling edge of STB.
Also, setting the SRC pin to high level allows the bias current value of the output amplifier to rise temporarily, and
setting the ORC pin to high level allows the output resistance value of the amplifier to lower temporarily.
For the timing and the processing of STB, SRC, or ORC during a high-level period, We recommend a thorough
evaluation of the LCD panel specifications in advance.
(1) When MODE is high level or left open
STB
SRC
High-slew-rate period
Low-slew-rate period
ORC
POL
High output resistance period
Low output resistance period
S2n–1
5
S2n
Voltage selected form V0 to V7
Voltage selected form V8 to V15
Voltage selected form V0 to V7
Voltage selected form V8 to V15
Voltage selected form V0 to V7
Voltage selected form V8 to V15
Hi-Z
Hi-Z
Hi-Z
16
DataSheet S14791EJ1V0DS