PD16721_15 Datasheet, PDF (6/30 Pages) Renesas Technology Corp – 384-OUTPUT TFT-LCD SOURCE DRIVER (COMPATIBLE WITH 256-GRAY SCALES)

µPD16721
4. PIN FUNCTIONS
Pin Symbol
S1 to S384
D00 to D07
Pin Name
Driver
Port 1 display data
D10 to D17
D20 to D27
D30 to D37
D40 to D47
D50 to D57
R,/L
Port 2 display data
Shift direction control
STHR
Right shift start pulse
STHL
Left shift start pulse
CLK
Shift clock
STB
Latch
SRC
ORC
POL
Slew-rate control
Output resistance control
Polarity input
(1/2)
I/O
Description
O The D/A converted 256-gray-scale analog voltage is output.
I
The display data is input with a width of 48 bits, viz., the gray scale
data
(8 bits) by 6 dots (2 pixels).
DX0: LSB, DX7: MSB
I
I
The shift direction control pin of shift register. The shift directions of
the shift registers are as follows.
R,/L = H (right shift): STHR input, S1→S384, STHL output
R,/L = L (left shift) : STHL input, S384→S1, STHR output
I/O This is the start pulse input/output pin when connected in cascade.
Loading of display data starts when a high level is read at the rising
edge of CLK.
At the rising edge of the 64th clock after the start pulse input, the start
I/O pulse output reaches the high level, thus becoming the start pulse of
the next-level driver.
For right shift, STHR is input and STHL is output.
For left shift, STHL is input and STHR is output.
I
The shift clock input pin of shift register. The display data is loaded
into the data register at the rising edge.
If 66 clock pulses are input after input of the start pulse, input of
display data is halted automatically. The contents of the shift register
are cleared at the STB’s rising edge.
I
The contents of the data register are transferred to the latch circuit at
the rising edge. In addition, at the falling edge, the gray scale voltage
is supplied to the driver. It is necessary to ensure input of one pulse
per horizontal period.
I
SRC = H: High-slew-rate mode (large current consumption)
SRC = L: Low-slew-rate mode (small current consumption)
SRC is pulled up to the VDD1 in the LSI.
I
ORC = H: Low output resistance mode
ORC = L: High output resistance mode
ORC is pulled up to the VDD1 in the LSI.
I
POL = L: The S2n−1 output uses V0 to V7 as the reference supply. The
S2n output uses V8 to V15 as the reference supply.
POL = H: The S2n−1 output uses V8 to V15 as the reference supply. The
S2n output uses V0 to V7 as the reference supply.
S2n−1 indicates the odd output and S2n indicates the even output. Input
of the POL signal is allowed the setup time (tPOL–STB) with respect to
STB’s rising edge.
When it switches such as POL = H→L or L→H, all output pins are
output reset during STB = H. When it does not switch, all output pins
become Hi-Z during STB = H. Refer to 7. RELATIONSHIP BETWEEN
MODE, STB, SRC, ORC, POL, AND OUTPUT WAVEFORM for
details.
4
DataSheet S14791EJ1V0DS