HD74LV595A Datasheet, PDF (7/14 Pages) Hitachi Semiconductor – 8-bit Shift Registers with 3-state Outputs

HD74LV595A
Switching Characteristics (cont)
Item
Maximum
clock frequency
Propagation
delay time
Enable time
Disable time
Setup time
Hold time
Pulse width
Symbol
f_max
t_PLH/t_PHL
t_PHL
t_ZH
t_ZL
t_HZ
t_LZ
t_SU
t_h
t_w
Ta = 25°C
Min Typ
80 150
55 130
— 8.8
— 11.3
— 7.7
— 10.2
— 8.4
— 10.9
— 7.5
— 9.0
— 5.9
— 12.1
3.5 —
8.0 —
8.0 —
3.0 —
1.5 —
0.0 —
0.0 —
5.0 —
5.0 —
5.0 —
Max
—
—
13.0
16.5
11.9
15.4
12.8
16.3
11.5
15.0
11.7
15.7
—
—
—
—
—
—
—
—
—
—
Ta = –40 to 85°C
Min Max
Unit
70
—
MHz
50
—
1.0 15.0
ns
1.0 18.5
1.0 13.5
1.0 17.0
1.0 13.7
1.0 17.2
1.0 13.5
ns
1.0 17.0
1.0 13.5
ns
1.0 16.2
3.5 —
ns
8.5 —
9.0 —
3.0 —
1.5 —
ns
0.0 —
0.0 —
5.0 —
ns
5.0 —
5.0 —
Test
Conditions
C_L = 15 pF
C_L = 50 pF
C_L = 15 pF
C_L = 50 pF
C_L = 15 pF
C_L = 50 pF
C_L = 15 pF
C_L = 50 pF
C_L = 15 pF
C_L = 50 pF
C_L = 15 pF
C_L = 50 pF
FROM
(Input)
V_CC = 3.3 ± 0.3 V
TO
(Output)
SRCLK
RCLK
SRCLK
G
Q_H'
Q_A – Q_H
Q_H'
Q_A – Q_H
SER before SRCLK ↑
SRCLK ↑ before RCLK ↑
SRCLR low before RCLK ↑
SRCLR high (inactive)
before SRCLK ↑
SER after SRCLK ↑
SRCLK ↑ after RCLK ↑
SRCLR low after RCLK ↑
RCLK high or low
SRCLK high or low
SRCLR low
Rev.2.00 Jun. 28, 2004 page 7 of 13