HD74LV595A Datasheet, PDF (6/14 Pages) Hitachi Semiconductor – 8-bit Shift Registers with 3-state Outputs

HD74LV595A
Switching Characteristics
Item
Maximum
clock frequency
Propagation
delay time
Enable time
Disable time
Setup time
Hold time
Pulse width
Symbol
f_max
t_PLH/t_PHL
t_PHL
t_ZH
t_ZL
t_HZ
t_LZ
t_SU
t_h
t_w
Ta = 25°C
Min Typ
65 80
60 70
— 11.6
— 14.8
— 10.5
— 13.7
— 11.2
— 14.4
— 10.3
— 12.2
— 7.6
— 14.4
5.5 —
10.0 —
10.0 —
5.0 —
2.0 —
0.5 —
0.5 —
7.0 —
7.0 —
6.0 —
Max
—
—
16.4
19.4
15.3
18.3
16.2
19.2
14.8
17.7
11.5
18.2
—
—
—
—
—
—
—
—
—
—
Ta = –40 to 85°C
Min
Max
Unit
45
—
MHz
40
—
1.0
19.5 ns
1.0
22.5
1.0
18.0
1.0
21.0
1.0
18.2
1.0
21.2
1.0
17.5 ns
1.0
20.5
1.0
13.5 ns
1.0
19.2
5.5
—
ns
10.5 —
11.0 —
5.0
—
2.0
—
ns
0.5
—
0.5
—
7.5
—
ns
7.5
—
6.5
—
Test
Conditions
C_L = 15 pF
C_L = 50 pF
C_L = 15 pF
C_L = 50 pF
C_L = 15 pF
C_L = 50 pF
C_L = 15 pF
C_L = 50 pF
C_L = 15 pF
C_L = 50 pF
C_L = 15 pF
C_L = 50 pF
FROM
(Input)
V_CC = 2.5 ± 0.2 V
TO
(Output)
SRCLK
RCLK
SRCLK
G
Q_H'
Q_A – Q_H
Q_H'
Q_A – Q_H
SER before SRCLK ↑
SRCLK ↑ before RCLK ↑
SRCLR low before RCLK ↑
SRCLR high (inactive)
before SRCLK ↑
SER after SRCLK ↑
SRCLK ↑ after RCLK ↑
SRCLR low after RCLK ↑
RCLK high or low
SRCLK high or low
SRCLR low
Rev.2.00 Jun. 28, 2004 page 6 of 13