HD74LV595A Datasheet, PDF (1/14 Pages) Hitachi Semiconductor – 8-bit Shift Registers with 3-state Outputs

HD74LV595A
8-bit Shift Registers with 3-state Outputs
REJ03D0335–0200Z
(Previous ADE-205-281 (Z))
Rev.2.00
Jun. 28, 2004
Description
This device each contains an 8-bit serial-in, parallel-out shift registers that feeds an 8-bit D-type storage register. The
storage register has parallel 3-state outputs. Separate clocks are provided for both the shift register and the storage
register. The shift register has a direct-overriding clear, serial input, and serial output pins for cascading.
Both the shift register and the storage register clocks are positive-edge triggered. If the user wishes to connect both
clocks together, the shift register state will always be one clock pulse ahead of the storage register. Low-voltage and
high-speed operation is suitable for the battery-powered products (e.g., notebook computers), and the low-power
consumption extends the battery life.
Features
• V_CC = 2.0 V to 5.5 V operation
• All inputs V_IH (Max.) = 5.5 V (@V_CC = 0 V to 5.5 V)
• All outputs V_O (Max.) = 5.5 V (@V_CC = 0 V)
• Typical V_OL ground bounce < 0.8 V (@V_CC = 3.3 V, Ta = 25°C)
• Typical V_OH undershoot > 2.3 V (@V_CC = 3.3 V, Ta = 25°C)
• Output current ±6 mA (@V_CC = 3.0 V to 3.6 V), ±12 mA (@V_CC = 4.5 V to 5.5 V)
• Ordering Information
Part Name
Package Type
Package Code
Package
Abbreviation
HD74LV595AFPEL
SOP–16 pin (JEITA) FP–16DAV
FP
HD74LV595ARPEL
SOP–16 pin (JEDEC) FP–16DNV
RP
HD74LV595ATELL
TSSOP–16 pin
TTP–16DAV
T
Note: Please consult the sales office for the above package availability.
Taping Abbreviation
(Quantity)
EL (2,000 pcs/reel)
EL (2,500 pcs/reel)
ELL (2,000 pcs/reel)
Function Table
Inputs
SER
SRCLK SRCLR RCLK
G
X
X
X
X
H
X
X
X
X
L
X
X
L
X
X
L
↑
H
X
X
H
↑
H
X
X
X
↓
H
X
X
X
X
X
↑
X
X
X
X
↓
X
Note: H: High level
L: Low level
X: Immaterial
↑: Low to high transition
↓: High to low transition
Function
Force outputs into high-impedance state
Enable parallel output
Reset shift register
Shift data into shift register
Shift data into shift register
Shift register remains unchanged
Transfer shift register contents to latch register
Latch register remains unchanged
Rev.2.00 Jun. 28, 2004 page 1 of 13