H8S2282 Datasheet, PDF (69/615 Pages) Renesas Technology Corp – 16-Bit Single-Chip Microcomputer H8S Family/H8S/2200 Series

Section 2 CPU
2.6 Instruction Set
The H8S/2000 CPU has 65 instructions. The instructions are classified by function in table 2.1.
Table 2.1 Instruction Classification
Function
Instructions
Size Types
Data transfer
MOV
POP^*1, PUSH^*1
B/W/L 5
W/L
LDM, STM
L
MOVFPE^*3, MOVTPE^*3
B
Arithmetic
operations
ADD, SUB, CMP, NEG
ADDX, SUBX, DAA, DAS
B/W/L 19
B
INC, DEC
B/W/L
ADDS, SUBS
L
MULXU, DIVXU, MULXS, DIVXS
B/W
EXTU, EXTS
W/L
TAS^*4
B
Logic operations AND, OR, XOR, NOT
B/W/L 4
Shift
SHAL, SHAR, SHLL, SHLR, ROTL, ROTR, ROTXL, ROTXR B/W/L 8
Bit manipulation BSET, BCLR, BNOT, BTST, BLD, BILD, BST, BIST, BAND, B
14
BIAND, BOR, BIOR, BXOR, BIXOR
Branch
Bcc^*2, JMP, BSR, JSR, RTS
—
5
System control
TRAPA, RTE, SLEEP, LDC, STC, ANDC, ORC, XORC, NOP —
9
Block data transfer EEPMOV
—
1
Total: 65
Legend:
B:
Byte
W: Word
L:
Longword
Notes: 1. POP.W Rn and PUSH.W Rn are identical to MOV.W @SP+, Rn and MOV.W Rn,
@-SP. POP.L ERn and PUSH.L ERn are identical to MOV.L @SP+, ERn and MOV.L
ERn, @-SP.
2. Bcc is the general name for conditional branch instructions.
3. Cannot be used in this LSI.
4. Only register ER0, ER1, ER4, or ER5 should be used when using the TAS instruction.
Rev. 3.00 Sep 26, 2006 page 37 of 580
REJ09B0148-0300