H8S2282 Datasheet, PDF (270/615 Pages) Renesas Technology Corp – 16-Bit Single-Chip Microcomputer H8S Family/H8S/2200 Series

Section 9 Watchdog Timer
9.5 Usage Notes
9.5.1 Notes on Register Access
The watchdog timer’s TCNT, TCSR, and RSTCSR registers differ from other registers in being
more difficult to write to. The procedures for writing to and reading these registers are given
below.
Writing to TCNT, TCSR, and RSTCSR
These registers must be written to by a word transfer instruction. They cannot be written to by a
byte transfer instruction.
TCNT and TCSR both have the same write address. Therefore, the relative condition shown in
figure 9.5 needs to be satisfied in order to write to TCNT or TCSR. The transfer instruction writes
the lower byte data to TCNT or TCSR according to the satisfied condition.
To write to RSTCSR, execute a word transfer instruction for address H'FF76. A byte transfer
instruction cannot write to RSTCSR.
The method of writing 0 to the WOVF bit differs from that of writing to the RSTE and RSTS bits.
To write 0 to the WOVF bit, satisfy the condition shown in figure 9.5. If satisfied, the transfer
instruction clears the WOVF bit to 0, but has no effect on the RSTE and RSTS bits. To write to
the RSTE and RSTS bits, satisfy the condition shown in figure 9.5. If satisfied, the transfer
instruction writes the values in bits 5 and 6 of the lower byte into the RSTE and RSTS bits,
respectively, but has no effect on the WOVF bit.
TCNT write
Writing to RSTE and RSTS bits
Address:
15
H'FF74
H'FF76
H'5A
87
0
Write data
TCSR write
Writing 0 to WOVF bit
15
Address: H'FF74
H'FF76
H'5A
87
0
Write data or H'00
Figure 9.5 Writing to TCNT, TCSR, and RSTCSR (example for WDT0)
Rev. 3.00 Sep 26, 2006 page 238 of 580
REJ09B0148-0300